linux-kernel - RE: [PATCH] i2c-designware: Mask interrupts during i2c controller enable

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <7286EAF50D3F4E4AADE7FEECEBF8B5A537A72207@ORSMSX109.amr.corp.intel.com>
Date:	Mon, 7 Apr 2014 16:48:02 +0000
From:	"Du, Wenkai" <wenkai.du@...el.com>
To:	"Westerberg, Mika" <mika.westerberg@...el.com>,
	One Thousand Gnomes <gnomes@...rguk.ukuu.org.uk>
CC:	"linux-i2c@...r.kernel.org" <linux-i2c@...r.kernel.org>,
	Wolfram Sang <wsa@...-dreams.de>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH] i2c-designware: Mask interrupts during i2c controller
 enable

> -----Original Message-----
> From: Westerberg, Mika
> Sent: Monday, April 07, 2014 8:11 AM
> To: One Thousand Gnomes
> Cc: Du, Wenkai; linux-i2c@...r.kernel.org; Wolfram Sang; linux-kernel@...r.kernel.org
> Subject: Re: [PATCH] i2c-designware: Mask interrupts during i2c controller enable
> 
> 
> Do you think we can fix it with adding a dummy read right after write to the mask register, like
> the snippet below?
> 
> diff --git a/drivers/i2c/busses/i2c-designware-core.c b/drivers/i2c/busses/i2c-designware-
> core.c
> index 14c4b30d4ccc..ff9090381d8b 100644
> --- a/drivers/i2c/busses/i2c-designware-core.c
> +++ b/drivers/i2c/busses/i2c-designware-core.c
> @@ -535,6 +535,7 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
>  		intr_mask = 0;
> 
>  	dw_writel(dev, intr_mask,  DW_IC_INTR_MASK);
> +	dw_readl(dev, DW_IC_INTR_MASK);
>  }
> 

I have tried this read back earlier during debugging, it didn't help. You can confirm yourself as well.

On the ISR code execution path, here is the list to my understanding:

1. TX abort: this path masks all interrupt by writing 0 to interrupt mask register;
2. RX full: this path doesn't do anything on masking interrupts;
3. TX empty: this path only mask TX empty under certain conditions; it doesn't mask other interrupt sources;
4. i2c STOP condition: this path call complete() to finish the transfer; it doesn't do anything on masking interrupts;

The above analysis agrees with the debug logs: most of interrupts are left unmasked in original code when i2c core is being enabled.

I think we want all interrupts masked when enabling HW. This will ensure the required 25us core turn on delay being respected. Also there could be spurious interrupts when HW is being turned on that should be ignored.

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/