linux-kernel - Re: [PATCH 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM controller

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Message-ID: <CANk1AXR0bDENDV673M-AVXNWHmGuee5SGc+ZnPqdBdEBwJXQXQ@mail.gmail.com>
Date:	Tue, 8 Apr 2014 11:02:15 -0500
From:	delicious quinoa <delicious.quinoa@...il.com>
To:	Steffen Trumtrar <s.trumtrar@...gutronix.de>
Cc:	Thor Thayer <tthayer@...era.com>,
	Rob Herring <robherring2@...il.com>, dougthompson@...ssion.com,
	Grant Likely <grant.likely@...aro.org>, pawel.moll@....com,
	Mark Rutland <mark.rutland@....com>,
	ijc+devicetree@...lion.org.uk, galak@...eaurora.org,
	Rob Landley <rob@...dley.net>, linux@....linux.org.uk,
	Dinh Nguyen <dinguyen@...era.com>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	linux-kernel <linux-kernel@...r.kernel.org>,
	linux-arm-kernel@...ts.infradead.org,
	"linux-doc@...r.kernel.org" <linux-doc@...r.kernel.org>
Subject: Re: [PATCH 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM controller

On Tue, Apr 8, 2014 at 9:33 AM, Steffen Trumtrar
<s.trumtrar@...gutronix.de> wrote:
> On Tue, Apr 08, 2014 at 09:29:50AM -0500, Thor Thayer wrote:
>> On Tue, 2014-04-08 at 15:38 +0200, Steffen Trumtrar wrote:
>> > Hi!
>> >
>> > On Mon, Apr 07, 2014 at 04:54:07PM -0500, tthayer@...era.com wrote:
>> > > From: Thor Thayer <tthayer@...era.com>
>> > >
>> > > Addition of the Altera SDRAM controller bindings and device
>> > > tree changes to the Altera SoC project.
>> > >
>> [snip]
>> > > +
>> > > +Required properties:
>> > > +- compatible : "altr,sdr-ctl", "syscon";
>> > > +                Note that syscon is invoked for this device to support the FPGA
>> > > +         bridge driver, EDAC driver and other devices that share the
>> > > +         registers.
>> > > +- reg : Should contain 1 register ranges(address and length)
>> >
>> > I haven't really thought this through, but why would the FPGA bridge driver
>> > access the sdram controller? For releasing the resets in fpgaportrst ? Or is
>> > there more?
>>
>> Hi Steffan. No, not for resets. We need to enable the FPGA to SDRAM
>> path. Our SDRAM controller allows FPGA master access to the SDRAM.
>>
>
> Yes. But what you have to do to enable the path is let the FPGA port you use
> out of reset. And that is it as far as I can see. The rest happens in the
> bitstream. Or is there more to enable the path?
> The FPGA2SDRAM bridge is the one I didn't use as of yet, so if I miss something
> please elaborate.

Hi Steffen,

The sdram controller is used by two drivers.  That's why we want to
specify "syscon" here.  The other driver is the FPGA bridge driver.
Its functionality is very separate from what this driver is doing (we
are not enabling the bridge in this driver; we are enabling the
monitoring and resetting the interrupt bit of the EDAC).  We wanted to
specify "syscon" her so that we don't have to have to change it for
the other driver.

Alan Tull
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