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Message-Id: <1397051478-4113-13-git-send-email-boris.brezillon@free-electrons.com>
Date:	Wed,  9 Apr 2014 15:51:15 +0200
From:	Boris BREZILLON <boris.brezillon@...e-electrons.com>
To:	Randy Dunlap <rdunlap@...radead.org>,
	Maxime Ripard <maxime.ripard@...e-electrons.com>,
	Emilio López <emilio@...pez.com.ar>,
	Mike Turquette <mturquette@...aro.org>,
	Linus Walleij <linus.walleij@...aro.org>
Cc:	devicetree@...r.kernel.org, linux-doc@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
	Boris BREZILLON <boris.brezillon@...e-electrons.com>
Subject: [PATCH 12/15] pinctrl: sunxi: retrieve and enable PL clk gate for A31 SoC

Retrieve and enable the clock gate related to PL pins.

Signed-off-by: Boris BREZILLON <boris.brezillon@...e-electrons.com>
---
 drivers/pinctrl/pinctrl-sunxi.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
index 64dffc8..da76ceb 100644
--- a/drivers/pinctrl/pinctrl-sunxi.c
+++ b/drivers/pinctrl/pinctrl-sunxi.c
@@ -898,6 +898,13 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
 			return -ENOMEM;
 
 		pctl->get_membase = sun6i_a31_pinctrl_get_membase;
+		clk = devm_clk_get(&pdev->dev, "pioL_clk");
+		if (IS_ERR(clk))
+			return PTR_ERR(clk);
+
+		ret = clk_prepare_enable(clk);
+		if (ret)
+			return ret;
 	} else {
 		pctl->get_membase = sunxi_pinctrl_get_membase;
 	}
-- 
1.8.3.2

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