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Message-ID: <20140409144940.GE28585@lukather>
Date: Wed, 9 Apr 2014 16:49:40 +0200
From: Maxime Ripard <maxime.ripard@...e-electrons.com>
To: Boris BREZILLON <boris.brezillon@...e-electrons.com>
Cc: Randy Dunlap <rdunlap@...radead.org>,
Emilio López <emilio@...pez.com.ar>,
Mike Turquette <mturquette@...aro.org>,
Linus Walleij <linus.walleij@...aro.org>,
devicetree@...r.kernel.org, linux-doc@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 05/15] clk: sunxi: add A31 APB0 clk gate defintions
On Wed, Apr 09, 2014 at 03:51:08PM +0200, Boris BREZILLON wrote:
> Add APB0 gates support for the A31 SoC.
> This gates are controlled by the PRCM (Power/Reset/Clock Management) block
> and thus will act on a different iomem range.
>
> Signed-off-by: Boris BREZILLON <boris.brezillon@...e-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@...e-electrons.com>
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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