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Message-ID: <CAGTfZH3Qnh_F8cHy+y9onvsuUxR+-F+3S=PgzGvsxdn0U1eGkw@mail.gmail.com>
Date: Sat, 12 Apr 2014 07:52:37 +0900
From: 최찬우 <cwchoi00@...il.com>
To: Tomasz Figa <t.figa@...sung.com>
Cc: Bartlomiej Zolnierkiewicz <b.zolnierkie@...sung.com>,
Chanwoo Choi <cw00.choi@...sung.com>,
linux-samsung-soc <linux-samsung-soc@...r.kernel.org>,
linux-iio@...r.kernel.org,
linux-kernel <linux-kernel@...r.kernel.org>,
Kyungmin Park <kyungmin.park@...sung.com>,
Kukjin Kim <kgene.kim@...sung.com>,
linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
ch.naveen@...sung.com, jic23@...nel.org
Subject: Re: [PATCH] iio: adc: exynos_adc: Control special clock of ADC to
support Exynos3250 ADC
Hi Tomasz,
On Fri, Apr 11, 2014 at 7:56 PM, Tomasz Figa <t.figa@...sung.com> wrote:
> Hi,
>
>
> On 11.04.2014 11:41, Bartlomiej Zolnierkiewicz wrote:
>>
>>
>> Hi,
>>
>> On Friday, April 11, 2014 11:00:40 AM Chanwoo Choi wrote:
>>>
>>> This patch control special clock for ADC in Exynos series's FSYS block.
>>
>>
>> s/control/controls/
>>
>>> If special clock of ADC is registerd on clock list of common clk
>>> framework,
>>> Exynos ADC drvier have to control this clock.
>>
>>
>> s/drvier/driver/
>>
>>> Exynos3250/Exynos4/Exynos5 has 'adc' clock as following:
>>> - 'adc' clock: bus clock for ADC
>>>
>>> Exynos3250 has additional 'sclk_tsadc' clock as following:
>>> - 'sclk_tsadc' clock: special clock for ADC which provide clock to
>>> internal ADC
>>>
>>> Exynos 4210/4212/4412 and Exynos5250/5420 has not included 'sclk_tsadc'
>>> clock
>>> in FSYS_BLK. But, Exynos3250 based on Cortex-A7 has only included
>>> 'sclk_tsadc'
>>> clock in FSYS_BLK.
>>>
>>> Cc: Jonathan Cameron <jic23@...nel.org>
>>> Cc: Kukjin Kim <kgene.kim@...sung.com>
>>> Cc: Naveen Krishna Chatradhi <ch.naveen@...sung.com>
>>> Cc: linux-iio@...r.kernel.org
>>> Signed-off-by: Chanwoo Choi <cw00.choi@...sung.com>
>>> Signed-off-by: Kyungmin Park <kyungmin.park@...sung.com>
>>> ---
>>> drivers/iio/adc/exynos_adc.c | 13 +++++++++++++
>>> 1 file changed, 13 insertions(+)
>
>
> This change alters DT bindings for Exynos ADC, so documentation must be
> modified appropriately.
OK, I'll add DT modification patch on next posting.
>
>
>>>
>>> diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c
>>> index d25b262..4cd1975 100644
>>> --- a/drivers/iio/adc/exynos_adc.c
>>> +++ b/drivers/iio/adc/exynos_adc.c
>>> @@ -88,6 +88,7 @@ struct exynos_adc {
>>> void __iomem *regs;
>>> void __iomem *enable_reg;
>>> struct clk *clk;
>>> + struct clk *sclk;
>>> unsigned int irq;
>>> struct regulator *vdd;
>>>
>>> @@ -308,6 +309,13 @@ static int exynos_adc_probe(struct platform_device
>>> *pdev)
>>> goto err_irq;
>>> }
>>>
>>> + info->sclk = devm_clk_get(&pdev->dev, "sclk_tsadc");
>>> + if (IS_ERR(info->sclk)) {
>>> + dev_warn(&pdev->dev, "failed getting sclk clock, err =
>>> %ld\n",
>>> +
>>> PTR_ERR(info->sclk));
>>> + info->sclk = NULL;
>>> + }
>>> +
>
>
> Is there any reason why we should have a warning on SoCs which don't have
> this clock? I think this clock should be acquired only for affected SoCs.
You are right.
As Sylwester comment on previous reply, I'll consider to use new compatible name
to handle clock in only proper SoC according to compatible name.
Best Regards,
Chanwoo Choi
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