lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <534BB90B.7030904@thomasmore.be>
Date:	Mon, 14 Apr 2014 12:31:39 +0200
From:	Bart Tanghe <bart.tanghe@...masmore.be>
To:	Tim Kryger <tim.kryger@...aro.org>,
	Stephen Warren <swarren@...dotorg.org>
CC:	Thierry Reding <thierry.reding@...il.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Linux PWM List <linux-pwm@...r.kernel.org>,
	linux-rpi-kernel@...ts.infradead.org
Subject: Re: [rfc]pwm: add BCM2835 PWM driver

Is it the responsibility of the pwm driver to handle the pinmux of the 
io pins? Or is the end user, or a parent driver responsible to handle this?
Idem for the clock?


On 04/09/2014 05:59 PM, Tim Kryger wrote:
> On Tue, Apr 8, 2014 at 6:27 PM, Stephen Warren <swarren@...dotorg.org> wrote:
>> On 04/08/2014 05:02 PM, Tim Kryger wrote:
>>> On Thu, Apr 3, 2014 at 6:44 AM, Bart Tanghe <bart.tanghe@...masmore.be> wrote:
>>>> need some recommendation
>>>> the memory mapped io registers of the bcm2835 pwm hardware are spreaded
>>>> over the memory mapped io
>>>> gpio config 0x20200004 - clk config 0x201010A0 - pwm configuration 0x2020C000
>>>> to handle this, I've used the base address of the memory mapped io
>>>> so I can use positive offsets
>>> So the registers for this PWM are located in three distinct memory regions?
>> ...
>>>> +struct bcm2835_pwm_chip {
>>>> +       struct pwm_chip chip;
>>>> +       struct device *dev;
>>>> +       int channel;
>>>> +       void __iomem *mmio;
>>> One pointer isn't going to be enough.  You need three.
>>>
>>> I suggest renaming the first and adding two more:
>>>
>>> void __iomem *base_pwm;
>>> void __iomem *base_clk;
>>> void __iomem *base_alt;
>> Sorry, I forgot about this patch. One comment here; the PWM driver can't
>> touch the clock or alt registers; those should be owned by the clock
>> driver, and the driver for whatever alt is (pinmux - don't recall what
>> it's touching there).
> Absolutely.  If these registers are owned by other drivers, go through them.

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ