linux-kernel - [tip:x86/urgent] x86/mm: In the PTE swapout page reclaim case clear the accessed bit instead of flushing the TLB

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Message-ID: <tip-b13b1d2d8692b437203de7a404c6b809d2cc4d99@git.kernel.org>
Date:	Wed, 16 Apr 2014 00:40:27 -0700
From:	tip-bot for Shaohua Li <tipbot@...or.com>
To:	linux-tip-commits@...r.kernel.org
Cc:	linux-kernel@...r.kernel.org, hpa@...or.com, mingo@...nel.org,
	a.p.zijlstra@...llo.nl, torvalds@...ux-foundation.org,
	hannes@...xchg.org, hughd@...gle.com, riel@...hat.com,
	shli@...ionio.com, mgorman@...e.de, tglx@...utronix.de,
	shli@...nel.org
Subject: [tip:x86/urgent] x86/mm:
  In the PTE swapout page reclaim case clear the accessed bit instead of flushing the TLB

Commit-ID:  b13b1d2d8692b437203de7a404c6b809d2cc4d99
Gitweb:     http://git.kernel.org/tip/b13b1d2d8692b437203de7a404c6b809d2cc4d99
Author:     Shaohua Li <shli@...nel.org>
AuthorDate: Tue, 8 Apr 2014 15:58:09 +0800
Committer:  Ingo Molnar <mingo@...nel.org>
CommitDate: Wed, 16 Apr 2014 08:57:08 +0200

x86/mm: In the PTE swapout page reclaim case clear the accessed bit instead of flushing the TLB

We use the accessed bit to age a page at page reclaim time,
and currently we also flush the TLB when doing so.

But in some workloads TLB flush overhead is very heavy. In my
simple multithreaded app with a lot of swap to several pcie
SSDs, removing the tlb flush gives about 20% ~ 30% swapout
speedup.

Fortunately just removing the TLB flush is a valid optimization:
on x86 CPUs, clearing the accessed bit without a TLB flush
doesn't cause data corruption.

It could cause incorrect page aging and the (mistaken) reclaim of
hot pages, but the chance of that should be relatively low.

So as a performance optimization don't flush the TLB when
clearing the accessed bit, it will eventually be flushed by
a context switch or a VM operation anyway. [ In the rare
event of it not getting flushed for a long time the delay
shouldn't really matter because there's no real memory
pressure for swapout to react to. ]

Suggested-by: Linus Torvalds <torvalds@...ux-foundation.org>
Signed-off-by: Shaohua Li <shli@...ionio.com>
Acked-by: Rik van Riel <riel@...hat.com>
Acked-by: Mel Gorman <mgorman@...e.de>
Acked-by: Hugh Dickins <hughd@...gle.com>
Acked-by: Johannes Weiner <hannes@...xchg.org>
Cc: linux-mm@...ck.org
Cc: Peter Zijlstra <a.p.zijlstra@...llo.nl>
Link: http://lkml.kernel.org/r/20140408075809.GA1764@kernel.org
[ Rewrote the changelog and the code comments. ]
Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
 arch/x86/mm/pgtable.c | 21 ++++++++++++++-------
 1 file changed, 14 insertions(+), 7 deletions(-)

diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c
index c96314a..0004ac7 100644
--- a/arch/x86/mm/pgtable.c
+++ b/arch/x86/mm/pgtable.c
@@ -399,13 +399,20 @@ int pmdp_test_and_clear_young(struct vm_area_struct *vma,
 int ptep_clear_flush_young(struct vm_area_struct *vma,
 			   unsigned long address, pte_t *ptep)
 {
-	int young;
-
-	young = ptep_test_and_clear_young(vma, address, ptep);
-	if (young)
-		flush_tlb_page(vma, address);
-
-	return young;
+	/*
+	 * On x86 CPUs, clearing the accessed bit without a TLB flush
+	 * doesn't cause data corruption. [ It could cause incorrect
+	 * page aging and the (mistaken) reclaim of hot pages, but the
+	 * chance of that should be relatively low. ]
+	 *
+	 * So as a performance optimization don't flush the TLB when
+	 * clearing the accessed bit, it will eventually be flushed by
+	 * a context switch or a VM operation anyway. [ In the rare
+	 * event of it not getting flushed for a long time the delay
+	 * shouldn't really matter because there's no real memory
+	 * pressure for swapout to react to. ]
+	 */
+	return ptep_test_and_clear_young(vma, address, ptep);
 }
 
 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
--
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