linux-kernel - Re: [PATCH v5 2/4] arm64: dts: APM X-Gene PCIe device tree nodes

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Message-ID: <20140416170545.GD4858@bart>
Date:	Wed, 16 Apr 2014 18:05:45 +0100
From:	"Liviu Dudau" <liviu@...au.co.uk>
To:	Rob Herring <robherring2@...il.com>
Cc:	Tanmay Inamdar <tinamdar@....com>,
	Bjorn Helgaas <bhelgaas@...gle.com>,
	Arnd Bergmann <arnd@...db.de>,
	Jason Gunthorpe <jgunthorpe@...idianresearch.com>,
	Grant Likely <grant.likely@...aro.org>,
	Rob Herring <robh+dt@...nel.org>,
	Catalin Marinas <catalin.marinas@....com>,
	Rob Landley <rob@...dley.net>,
	Liviu Dudau <liviu.dudau@....com>,
	"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"linux-doc@...r.kernel.org" <linux-doc@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"patches@....com" <patches@....com>,
	"jcm@...hat.com" <jcm@...hat.com>
Subject: Re: [PATCH v5 2/4] arm64: dts: APM X-Gene PCIe device tree nodes

On Wed, Mar 26, 2014 at 09:28:42AM -0500, Rob Herring wrote:
> On Wed, Mar 19, 2014 at 6:12 PM, Tanmay Inamdar <tinamdar@....com> wrote:
> > This patch adds the device tree nodes for APM X-Gene PCIe controller and
> > PCIe clock interface. Since X-Gene SOC supports maximum 5 ports, 5 dts
> > nodes are added.
> 
> [snip]
> 
> > +               pcie0: pcie@...b0000 {
> > +                       status = "disabled";
> > +                       device_type = "pci";
> > +                       compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
> > +                       #interrupt-cells = <1>;
> > +                       #size-cells = <2>;
> > +                       #address-cells = <3>;
> > +                       reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */
> > +                               0xe0 0xd0000000 0x0 0x00200000>; /* PCI config space */
> 

Resurecting an old thread as this is relevant to what I'm doing at the moment:

> Where is the right place for config space? This binding has it here
> and others have it in ranges. Given that config space type is defined
> for ranges, I would think that is the right place. But Liviu's patches
> do not process config space entries in ranges. Perhaps we need a
> config space resource populated in the bridge struct.

I have found out that we cannot pasd the config ranges from the DT into the
pci_host_bridge structure as the PCI framework doesn't have a resource type
for config resources. Leaving the translation between range flags and
resource type as is (filtered through the IORESOURCE_TYPE_BITS) will lead
to a resource type of value zero, which is not recognised by any resource
handling API so bridge configuration and bus scanning will barf.

I'm looking for suggestions here, as Jason Gunthorpe suggested that we
should be able to parse config ranges if they conform to the ECAM part
of the PCI standard.

Best regards,
Liviu

> 
> Rob
> 
> 
> > +                       reg-names = "csr", "cfg";
> > +                       ranges = <0x01000000 0x00 0x00000000 0xe0 0x00000000 0x00 0x00010000   /* io */
> > +                                 0x02000000 0x00 0x10000000 0xe0 0x10000000 0x00 0x80000000>; /* mem */
> --
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> 

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