linux-kernel - Re: [PATCH] PNP: Work around BIOS defects in Intel MCH area reporting

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Message-ID: <1702309.mG1EHfKp35@vostro.rjw.lan>
Date:	Mon, 21 Apr 2014 22:44:29 +0200
From:	"Rafael J. Wysocki" <rjw@...ysocki.net>
To:	Bjorn Helgaas <bhelgaas@...gle.com>
Cc:	Aaron Lu <aaron.lu@...el.com>, linux-pci@...r.kernel.org,
	x86@...nel.org, linux-kernel@...r.kernel.org,
	Stephane Eranian <eranian@...gle.com>,
	linux-acpi@...r.kernel.org, Borislav Petkov <bp@...en8.de>,
	"H. Peter Anvin" <hpa@...or.com>,
	Zheng Z Yan <zheng.z.yan@...el.com>,
	Dave Jones <davej@...hat.com>, Rui Zhang <rui.zhang@...el.com>,
	Yinghai Lu <yinghai@...nel.org>
Subject: Re: [PATCH] PNP: Work around BIOS defects in Intel MCH area reporting

Hi Bjorn,

On Thursday, April 17, 2014 02:20:33 PM Bjorn Helgaas wrote:
> Work around BIOSes that don't report the entire Intel MCH area.
> 
> MCHBAR is not an architected PCI BAR, so MCH space is usually reported as a
> PNP0C02 resource.  The MCH space was once 16KB, but is 32KB in newer parts.
> Some BIOSes still report a PNP0C02 resource that is only 16KB, which means
> the rest of the MCH space is consumed but unreported.
> 
> This can cause resource map sanity check warnings or (theoretically) a
> device conflict if we assigned the unreported space to another device.
> 
> The Intel perf event uncore driver tripped over this when it claimed the
> MCH region:
> 
>   resource map sanity check conflict: 0xfed10000 0xfed15fff 0xfed10000 0xfed13fff pnp 00:01
>   Info: mapping multiple BARs. Your kernel is fine.
> 
> To prevent this, if we find a PNP0C02 resource that covers part of the MCH
> space, extend it to cover the entire space.
> 
> Link: http://lkml.kernel.org/r/20140224162400.GE16457@pd.tnic
> Reported-by: Borislav Petkov <bp@...en8.de>
> Tested-by: Borislav Petkov <bp@...e.de>
> Signed-off-by: Bjorn Helgaas <bhelgaas@...gle.com>
> Acked-by: Borislav Petkov <bp@...e.de>

Do you want me to take this patch for PNP, or are you planning to take it
into your tree?

Rafael


> ---
>  drivers/pnp/quirks.c |   74 ++++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 74 insertions(+)
> 
> diff --git a/drivers/pnp/quirks.c b/drivers/pnp/quirks.c
> index 258fef272ea7..90b8c12c220d 100644
> --- a/drivers/pnp/quirks.c
> +++ b/drivers/pnp/quirks.c
> @@ -334,6 +334,79 @@ static void quirk_amd_mmconfig_area(struct pnp_dev *dev)
>  }
>  #endif
>  
> +/* Device IDs of parts that have 32KB MCH space */
> +static const unsigned int mch_quirk_devices[] = {
> +	0x0154,	/* Ivy Bridge */
> +	0x0c00,	/* Haswell */
> +};
> +
> +static struct pci_dev *get_intel_host(void)
> +{
> +	int i;
> +	struct pci_dev *host;
> +
> +	for (i = 0; i < ARRAY_SIZE(mch_quirk_devices); i++) {
> +		host = pci_get_device(PCI_VENDOR_ID_INTEL, mch_quirk_devices[i],
> +				      NULL);
> +		if (host)
> +			return host;
> +	}
> +	return NULL;
> +}
> +
> +static void quirk_intel_mch(struct pnp_dev *dev)
> +{
> +	struct pci_dev *host;
> +	u32 addr_lo, addr_hi;
> +	struct pci_bus_region region;
> +	struct resource mch;
> +	struct pnp_resource *pnp_res;
> +	struct resource *res;
> +
> +	host = get_intel_host();
> +	if (!host)
> +		return;
> +
> +	/*
> +	 * MCHBAR is not an architected PCI BAR, so MCH space is usually
> +	 * reported as a PNP0C02 resource.  The MCH space was originally
> +	 * 16KB, but is 32KB in newer parts.  Some BIOSes still report a
> +	 * PNP0C02 resource that is only 16KB, which means the rest of the
> +	 * MCH space is consumed but unreported.
> +	 */
> +
> +	/*
> +	 * Read MCHBAR for Host Member Mapped Register Range Base
> +	 * https://www-ssl.intel.com/content/www/us/en/processors/core/4th-gen-core-family-desktop-vol-2-datasheet
> +	 * Sec 3.1.12.
> +	 */
> +	pci_read_config_dword(host, 0x48, &addr_lo);
> +	region.start = addr_lo & ~0x7fff;
> +	pci_read_config_dword(host, 0x4c, &addr_hi);
> +	region.start |= (dma_addr_t) addr_hi << 32;
> +	region.end = region.start + 32*1024 - 1;
> +
> +	memset(&mch, 0, sizeof(mch));
> +	mch.flags = IORESOURCE_MEM;
> +	pcibios_bus_to_resource(host->bus, &mch, &region);
> +
> +	list_for_each_entry(pnp_res, &dev->resources, list) {
> +		res = &pnp_res->res;
> +		if (res->end < mch.start || res->start > mch.end)
> +			continue;	/* no overlap */
> +		if (res->start == mch.start && res->end == mch.end)
> +			continue;	/* exact match */
> +
> +		dev_info(&dev->dev, FW_BUG "PNP resource %pR covers only part of %s Intel MCH; extending to %pR\n",
> +			 res, pci_name(host), &mch);
> +		res->start = mch.start;
> +		res->end = mch.end;
> +		break;
> +	}
> +
> +	pci_dev_put(host);
> +}
> +
>  /*
>   *  PnP Quirks
>   *  Cards or devices that need some tweaking due to incomplete resource info
> @@ -364,6 +437,7 @@ static struct pnp_fixup pnp_fixups[] = {
>  #ifdef CONFIG_AMD_NB
>  	{"PNP0c01", quirk_amd_mmconfig_area},
>  #endif
> +	{"PNP0c02", quirk_intel_mch},
>  	{""}
>  };
>  
> 
> --
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-- 
I speak only for myself.
Rafael J. Wysocki, Intel Open Source Technology Center.
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