linux-kernel - [PATCH RFC 07/12] mmc: mmci: Qcomm: Add 3 clock cycle delay after each register write

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Message-Id: <1398116909-31517-1-git-send-email-srinivas.kandagatla@linaro.org>
Date:	Mon, 21 Apr 2014 22:48:29 +0100
From:	srinivas.kandagatla@...aro.org
To:	linux-mmc@...r.kernel.org
Cc:	Russell King <linux@....linux.org.uk>,
	Chris Ball <chris@...ntf.net>,
	Ulf Hansson <ulf.hansson@...aro.org>,
	linux-kernel@...r.kernel.org, agross@...cinc.com,
	linux-arm-msm@...r.kernel.org,
	Srinivas Kandagatla <srinivas.kandagatla@...aro.org>
Subject: [PATCH RFC 07/12] mmc: mmci: Qcomm: Add 3 clock cycle delay after each register write

From: Srinivas Kandagatla <srinivas.kandagatla@...aro.org>

This patch adds a 3 clock cycle delay required after writing to controller
registers on Qualcomm SOCs. Without this delay cards are either not detected
or fails as soon as card is put into data transfer mode.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@...aro.org>
---
 drivers/mmc/host/mmci.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 86bf330..2dc7581 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -168,6 +168,7 @@ static struct variant_data variant_qcom = {
 	.fifosize		= 16 * 4,
 	.fifohalfsize		= 8 * 4,
 	.clkreg			= MCI_CLK_ENABLE,
+	.reg_write_delay	= 3,
 	.blksz_datactrl4	= true,
 	.datalength_bits	= 24,
 	.blksz_datactrl4	= true,
-- 
1.7.9.5

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