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Message-Id: <1398263451-18023-3-git-send-email-gautam.vivek@samsung.com>
Date: Wed, 23 Apr 2014 20:00:44 +0530
From: Vivek Gautam <gautam.vivek@...sung.com>
To: linux-usb@...r.kernel.org, linux-samsung-soc@...r.kernel.org,
devicetree@...r.kernel.org
Cc: linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
kgene.kim@...sung.com, robh+dt@...nel.org,
gregkh@...uxfoundation.org, olof@...om.net, balbi@...com,
jg1.han@...sung.com, t.figa@...sung.com
Subject: [PATCH v5 2/9] dt: exynos5420: Enable support for DWC3 controller
Add device tree nodes for DWC3 controller present on
Exynos 5420 SoC, to enable support for USB 3.0.
Signed-off-by: Vivek Gautam <gautam.vivek@...sung.com>
Reviewed-by: Tomasz Figa <t.figa@...sung.com>
---
arch/arm/boot/dts/exynos5420.dtsi | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index f69745f..e808d1b 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -733,6 +733,23 @@
samsung,power-domain = <&g2d_pd>;
};
+ usb@...00000 {
+ compatible = "samsung,exynos5250-dwusb3";
+ clocks = <&clock CLK_USBD300>;
+ clock-names = "usbdrd30";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ dwc3 {
+ compatible = "synopsys,dwc3";
+ reg = <0x12000000 0x10000>;
+ interrupts = <0 72 0>;
+ phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+ };
+
usbdrd_phy0: phy@...00000 {
compatible = "samsung,exynos5420-usbdrd-phy";
reg = <0x12100000 0x100>;
@@ -743,6 +760,23 @@
#phy-cells = <1>;
};
+ usb@...00000 {
+ compatible = "samsung,exynos5250-dwusb3";
+ clocks = <&clock CLK_USBD301>;
+ clock-names = "usbdrd30";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ dwc3 {
+ compatible = "synopsys,dwc3";
+ reg = <0x12400000 0x10000>;
+ interrupts = <0 73 0>;
+ phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+ };
+
usbdrd_phy1: phy@...00000 {
compatible = "samsung,exynos5420-usbdrd-phy";
reg = <0x12500000 0x100>;
--
1.7.10.4
--
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