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Date:	Fri, 25 Apr 2014 12:47:04 +0800
From:	Huang Shijie <b32955@...escale.com>
To:	Graham Moore <ggrahammoore@...il.com>
CC:	Marek Vasut <marex@...x.de>,
	Geert Uytterhoeven <geert+renesas@...ux-m68k.org>,
	Insop Song <insop.song@...nspeed.com>,
	Graham Moore <grmoore@...era.com>,
	Sascha Hauer <s.hauer@...gutronix.de>,
	Jingoo Han <jg1.han@...sung.com>,
	<linux-kernel@...r.kernel.org>,
	Yves Vandervennet <rocket.yvanderv@...il.com>,
	<linux-mtd@...ts.infradead.org>,
	Artem Bityutskiy <artem.bityutskiy@...ux.intel.com>,
	Alan Tull <atull@...era.com>,
	Sourav Poddar <sourav.poddar@...com>,
	Brian Norris <computersforpeace@...il.com>,
	David Woodhouse <dwmw2@...radead.org>,
	Dinh Nguyen <dinguyen@...era.com>
Subject: Re: [PATCH V3] Add support for flag status register on Micron
 chips.

On Tue, Apr 22, 2014 at 01:48:21PM -0500, Graham Moore wrote:
> On Tue, Apr 22, 2014 at 11:55 AM, Marek Vasut <marex@...x.de> wrote:
> > Are you sure the n25q512a doesn't use FSR ? Do n25q512a{1,8}3 share the same
> > IDs?
> 
> I looked at the datasheet and the n25q512a *does* have the same FSR
> usage note, so I suppose I should add USE_FSR to it as well.  But how
> is it working now?  Maybe nobody is actually using that chip.
> Yes, n25q512a{1,8}3 share the same id, 0x20ba20.
> 
could use the ext_id to distinguish them ? just as we did for Spansion NOR.

i dumped out 5 bytes of my n25q256a: 0x20, 0xba, 0x19, 0x10, 0x00.

thanks
Huang Shijie
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