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Message-id: <1398584283-22846-32-git-send-email-shaik.ameer@samsung.com>
Date: Sun, 27 Apr 2014 13:08:03 +0530
From: Shaik Ameer Basha <shaik.ameer@...sung.com>
To: linux-samsung-soc@...r.kernel.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
iommu@...ts.linux-foundation.org, linux-kernel@...r.kernel.org
Cc: kgene.kim@...sung.com, tomasz.figa@...il.com,
pullip.cho@...sung.com, a.motakis@...tualopensystems.com,
grundler@...omium.org, joro@...tes.org, prathyush.k@...sung.com,
rahul.sharma@...sung.com, sachin.kamat@...aro.org,
supash.ramaswamy@...aro.org, Varun.Sethi@...escale.com,
s.nawrocki@...sung.com, t.figa@...sung.com, joshi@...sung.com,
Shaik Ameer Basha <shaik.ameer@...sung.com>
Subject: [PATCH v12 31/31] ARM: dts: add System MMU nodes of exynos5420
From: Cho KyongHo <pullip.cho@...sung.com>
This patch adds System MMU nodes of exynos5420 except
System MMUs in Image Subsystem.
Signed-off-by: Cho KyongHo <pullip.cho@...sung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@...sung.com>
---
arch/arm/boot/dts/exynos5420.dtsi | 209 ++++++++++++++++++++++++++++++++++++-
1 file changed, 206 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index c3a9a66..1fc0c9f 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -125,7 +125,7 @@
clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
};
- codec@...00000 {
+ mfc: codec@...00000 {
compatible = "samsung,mfc-v7";
reg = <0x11000000 0x10000>;
interrupts = <0 96 0>;
@@ -472,7 +472,7 @@
phy-names = "dp";
};
- fimd@...00000 {
+ fimd: fimd@...00000 {
samsung,power-domain = <&disp_pd>;
clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
clock-names = "sclk_fimd", "fimd";
@@ -644,7 +644,7 @@
status = "disabled";
};
- mixer@...50000 {
+ mixer: mixer@...50000 {
compatible = "samsung,exynos5420-mixer";
reg = <0x14450000 0x10000>;
interrupts = <0 94 0>;
@@ -732,4 +732,207 @@
clock-names = "secss";
samsung,power-domain = <&g2d_pd>;
};
+
+ sysmmu_g2dr: sysmmu@...60000 {
+ compatible = "samsung,sysmmu-v3.2";
+ reg = <0x10A60000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <24 5>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
+ };
+
+ sysmmu_g2dw: sysmmu@...70000 {
+ compatible = "samsung,sysmmu-v3.2";
+ reg = <0x10A70000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <22 2>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
+ };
+
+ sysmmu_scaler0r: sysmmu@...80000 {
+ compatible = "samsung,sysmmu-v3.2";
+ reg = <0x12880000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <22 4>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
+ };
+
+ sysmmu_scaler1r: sysmmu@...90000 {
+ compatible = "samsung,sysmmu-v3.2";
+ reg = <0x12890000 0x1000>;
+ interrupts = <0 186 0>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
+ };
+
+ sysmmu_scaler2r: sysmmu@...A0000 {
+ compatible = "samsung,sysmmu-v3.2";
+ reg = <0x128A0000 0x1000>;
+ interrupts = <0 188 0>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
+ };
+
+ sysmmu_scaler0w: sysmmu@...C0000 {
+ compatible = "samsung,sysmmu-v3.2";
+ reg = <0x128C0000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <27 2>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
+ };
+
+ sysmmu_scaler1w: sysmmu@...D0000 {
+ compatible = "samsung,sysmmu-v3.2";
+ reg = <0x128D0000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <22 6>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
+ };
+
+ sysmmu_scaler2w: sysmmu@...E0000 {
+ compatible = "samsung,sysmmu-v3.2";
+ reg = <0x128E0000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <19 6>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
+ };
+
+ sysmmu_mfc_l: sysmmu@...00000 {
+ compatible = "samsung,sysmmu-v2";
+ reg = <0x11200000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <8 5>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
+ mmu-masters = <&mfc>;
+ samsung,power-domain = <&mfc_pd>;
+ };
+
+ sysmmu_mfc_r: sysmmu@...10000 {
+ compatible = "samsung,sysmmu-v2";
+ reg = <0x11210000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <6 2>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
+ mmu-masters = <&mfc>;
+ samsung,power-domain = <&mfc_pd>;
+ };
+
+ sysmmu_rotator: sysmmu@...40000 {
+ compatible = "samsung,sysmmu-v3.1";
+ reg = <0x11D40000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <4 0>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
+ };
+
+ sysmmu_fimc_lite0: sysmmu@...40000 {
+ compatible = "samsung,sysmmu-v3.3";
+ reg = <0x13C40000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <3 4>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_FIMCL0>, <&clock CLK_FIMC_LITE0>;
+ samsung,power-domain = <&gsc_pd>;
+ };
+
+ sysmmu_fimc_lite1: sysmmu@...50000 {
+ compatible = "samsung,sysmmu-v3.3";
+ reg = <0x13C50000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <24 1>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_FIMCL1>, <&clock CLK_FIMC_LITE1>;
+ samsung,power-domain = <&gsc_pd>;
+ };
+
+ sysmmu_fimc_lite3: sysmmu@...50000 {
+ compatible = "samsung,sysmmu-v1";
+ reg = <0x13D50000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <2 4>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_FIMCL3>, <&clock CLK_FIMC_LITE3>;
+ samsung,power-domain = <&gsc_pd>;
+ };
+
+ sysmmu_gsc0: sysmmu@...80000 {
+ compatible = "samsung,sysmmu-v3.3";
+ reg = <0x13E80000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <2 0>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
+ samsung,power-domain = <&gsc_pd>;
+ mmu-masters = <&gsc_0>;
+ };
+
+ sysmmu_gsc1: sysmmu@...90000 {
+ compatible = "samsung,sysmmu-v3.3";
+ reg = <0x13E90000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <2 2>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
+ samsung,power-domain = <&gsc_pd>;
+ mmu-masters = <&gsc_1>;
+ };
+
+ sysmmu_fimd0w04: sysmmu@...40000 {
+ compatible = "samsung,sysmmu-v3.3";
+ reg = <0x14640000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <3 2>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
+ samsung,power-domain = <&disp_pd>;
+ mmu-masters = <&fimd>;
+ };
+
+ sysmmu_fimd0w123: sysmmu@...80000 {
+ compatible = "samsung,sysmmu-v3.3";
+ reg = <0x14680000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <3 0>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>;
+ samsung,power-domain = <&disp_pd>;
+ mmu-masters = <&fimd>;
+ };
+
+ sysmmu_tv: sysmmu@...50000 {
+ compatible = "samsung,sysmmu-v3.3";
+ reg = <0x14650000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <7 4>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>;
+ samsung,power-domain = <&disp_pd>;
+ mmu-masters = <&mixer>;
+ };
+
+ sysmmu_jpeg: sysmmu@...10000 {
+ compatible = "samsung,sysmmu-v1";
+ reg = <0x11F10000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <4 2>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
+ };
+
+ sysmmu_jpeg2: sysmmu@...20000 {
+ compatible = "samsung,sysmmu-v1";
+ reg = <0x11F20000 0x1000>;
+ interrupts = <0 169 0>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG2>;
+ };
};
--
1.7.9.5
--
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