linux-kernel - [PATCH 3.2 68/94] MIPS: Hibernate: Flush TLB entries in swsusp_arch

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Message-ID: <lsq.1398647482.427257962@decadent.org.uk>
Date:	Mon, 28 Apr 2014 02:11:22 +0100
From:	Ben Hutchings <ben@...adent.org.uk>
To:	linux-kernel@...r.kernel.org, stable@...r.kernel.org
CC:	akpm@...ux-foundation.org, "Ralf Baechle" <ralf@...ux-mips.org>,
	"John Crispin" <john@...ozen.org>,
	"Fuxin Zhang" <zhangfx@...ote.com>,
	"Zhangjin Wu" <wuzhangjin@...il.com>, linux-mips@...ux-mips.org,
	"Aurelien Jarno" <aurelien@...el32.net>,
	"Steven J. Hill" <Steven.Hill@...tec.com>,
	"Huacai Chen" <chenhc@...ote.com>
Subject: [PATCH 3.2 68/94] MIPS: Hibernate: Flush TLB entries in
 swsusp_arch_resume()

3.2.58-rc1 review patch.  If anyone has any objections, please let me know.

------------------

From: Huacai Chen <chenhc@...ote.com>

commit c14af233fbe279d0e561ecf84f1208b1bae087ef upstream.

The original MIPS hibernate code flushes cache and TLB entries in
swsusp_arch_resume(). But they are removed in Commit 44eeab67416711
(MIPS: Hibernation: Remove SMP TLB and cacheflushing code.). A cross-
CPU flush is surely unnecessary because all but the local CPU have
already been disabled. But a local flush (at least the TLB flush) is
needed. When we do hibernation on Loongson-3 with an E1000E NIC, it is
very easy to produce a kernel panic (kernel page fault, or unaligned
access). The root cause is E1000E driver use vzalloc_node() to allocate
pages, the stale TLB entries of the booting kernel will be misused by
the resumed target kernel.

Signed-off-by: Huacai Chen <chenhc@...ote.com>
Cc: John Crispin <john@...ozen.org>
Cc: Steven J. Hill <Steven.Hill@...tec.com>
Cc: Aurelien Jarno <aurelien@...el32.net>
Cc: linux-mips@...ux-mips.org
Cc: Fuxin Zhang <zhangfx@...ote.com>
Cc: Zhangjin Wu <wuzhangjin@...il.com>
Patchwork: https://patchwork.linux-mips.org/patch/6643/
Signed-off-by: Ralf Baechle <ralf@...ux-mips.org>
Signed-off-by: Ben Hutchings <ben@...adent.org.uk>
---
 arch/mips/power/hibernate.S | 1 +
 1 file changed, 1 insertion(+)

--- a/arch/mips/power/hibernate.S
+++ b/arch/mips/power/hibernate.S
@@ -44,6 +44,7 @@ LEAF(swsusp_arch_resume)
 	bne t1, t3, 1b
 	PTR_L t0, PBE_NEXT(t0)
 	bnez t0, 0b
+	jal local_flush_tlb_all /* Avoid TLB mismatch after kernel resume */
 	PTR_LA t0, saved_regs
 	PTR_L ra, PT_R31(t0)
 	PTR_L sp, PT_R29(t0)

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