linux-kernel - [PATCH 2/4] ARM: dts: Add usb2phy to Exynos 5250

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Message-Id: <1398848110-6152-3-git-send-email-gautam.vivek@samsung.com>
Date:	Wed, 30 Apr 2014 14:25:08 +0530
From:	Vivek Gautam <gautam.vivek@...sung.com>
To:	linux-usb@...r.kernel.org, linux-samsung-soc@...r.kernel.org
Cc:	linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org, kgene.kim@...sung.com,
	stern@...land.harvard.edu, kishon@...com, k.debski@...sung.com,
	jg1.han@...sung.com, p.paneri@...sung.com,
	Vivek Gautam <gautam.vivek@...sung.com>
Subject: [PATCH 2/4] ARM: dts: Add usb2phy to Exynos 5250

From: Kamil Debski <k.debski@...sung.com>

Add support to PHY of USB2 of the Exynos 5250 SoC.

Signed-off-by: Kamil Debski <k.debski@...sung.com>
[gautam.vivek@...sung.com: Split the usb phy entries from
syscon entries from earlier patch: dts: Add usb2phy to Exynos 5250]
[gautam.vivek@...sung.com: Added phy entry for OHCI also along with EHCI]
Signed-off-by: Vivek Gautam <gautam.vivek@...sung.com>
---

Changes from v7:
None

 arch/arm/boot/dts/exynos5250.dtsi |   26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 70f0cd5..51e554c 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -563,6 +563,14 @@
 
 		clocks = <&clock CLK_USB2>;
 		clock-names = "usbhost";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port@0 {
+			reg = <0>;
+			phys = <&usb2_phy_gen 1>;
+			phy-names = "host";
+			status = "ok";
+		};
 	};
 
 	usb@...20000 {
@@ -572,6 +580,14 @@
 
 		clocks = <&clock CLK_USB2>;
 		clock-names = "usbhost";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port@0 {
+			reg = <0>;
+			phys = <&usb2_phy_gen 1>;
+			phy-names = "host";
+			status = "ok";
+		};
 	};
 
 	usb2_phy: usbphy@...30000 {
@@ -589,6 +605,16 @@
 		};
 	};
 
+	usb2_phy_gen: phy@...30000 {
+		compatible = "samsung,exynos5250-usb2-phy";
+		reg = <0x12130000 0x100>;
+		clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
+		clock-names = "phy", "ref";
+		#phy-cells = <1>;
+		samsung,sysreg-phandle = <&sysreg_system_controller>;
+		samsung,pmureg-phandle = <&pmu_system_controller>;
+	};
+
 	pwm: pwm@...d0000 {
 		compatible = "samsung,exynos4210-pwm";
 		reg = <0x12dd0000 0x100>;
-- 
1.7.10.4

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