linux-kernel - Re: [PATCH v8 17/20] usb: phy: msm: Select secondary PHY via TCSR

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Date:	Wed, 30 Apr 2014 11:23:18 -0500
From:	Felipe Balbi <balbi@...com>
To:	"Ivan T. Ivanov" <iivanov@...sol.com>
CC:	Felipe Balbi <balbi@...com>, Tim Bird <tbird20d@...il.com>,
	Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
	<linux-usb@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
	<linux-arm-msm@...r.kernel.org>, Tim Bird <tim.bird@...ymobile.com>
Subject: Re: [PATCH v8 17/20] usb: phy: msm: Select secondary PHY via TCSR

On Mon, Apr 28, 2014 at 04:34:20PM +0300, Ivan T. Ivanov wrote:
> From: Tim Bird <tbird20d@...il.com>
> 
> Select the secondary PHY using the TCSR register, if phy-num=1
> in the DTS (or phy_number is set in the platform data).  The
> SOC has 2 PHYs which can be used with the OTG port, and this
> code allows configuring the correct one.
> 
> Note: This resolves the problem I was seeing where I couldn't
> get the USB driver working at all on a dragonboard, from cold
> boot.  This patch depends on patch 5/14 from Ivan's msm USB
> patch set.  It does not use DT for the register address, as
> there's no evidence that this address changes between SoC
> versions.
> 
> Signed-off-by: Tim Bird <tim.bird@...ymobile.com>
> ---
>  drivers/usb/phy/phy-msm-usb.c    | 14 ++++++++++++++
>  include/linux/usb/msm_hsusb_hw.h |  3 +++
>  2 files changed, 17 insertions(+)
> 
> diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy/phy-msm-usb.c
> index db8d963..9437bcf 100644
> --- a/drivers/usb/phy/phy-msm-usb.c
> +++ b/drivers/usb/phy/phy-msm-usb.c
> @@ -1489,6 +1489,7 @@ static int msm_otg_probe(struct platform_device *pdev)
>  	struct resource *res;
>  	struct msm_otg *motg;
>  	struct usb_phy *phy;
> +	void __iomem *phy_select;
> 
>  	motg = devm_kzalloc(&pdev->dev, sizeof(struct msm_otg), GFP_KERNEL);
>  	if (!motg) {
> @@ -1553,6 +1554,19 @@ static int msm_otg_probe(struct platform_device *pdev)
>  	if (IS_ERR(motg->regs))
>  		return PTR_ERR(motg->regs);
> 
> +	/*
> +	 * NOTE: The PHYs can be multiplexed between the chipidea controller
> +	 * and the dwc3 controller, using a single bit. It is important that
> +	 * the dwc3 driver does not set this bit in an incompatible way.

why would dwc3 access the PHY's address space ?

-- 
balbi

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