linux-kernel - Re: 64bit x86: NMI nesting still buggy?

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Message-ID: <53617D54.2060709@linux.intel.com>
Date:	Wed, 30 Apr 2014 15:46:44 -0700
From:	"H. Peter Anvin" <hpa@...ux.intel.com>
To:	Jiri Kosina <jkosina@...e.cz>
CC:	Steven Rostedt <rostedt@...dmis.org>,
	Linus Torvalds <torvalds@...ux-foundation.org>,
	linux-kernel@...r.kernel.org, x86@...nel.org,
	Salman Qazi <sqazi@...gle.com>, Ingo Molnar <mingo@...e.hu>,
	Michal Hocko <mhocko@...e.cz>, Borislav Petkov <bp@...en8.de>,
	Vojtech Pavlik <vojtech@...e.cz>,
	Petr Tesarik <ptesarik@...e.cz>, Petr Mladek <pmladek@...e.cz>
Subject: Re: 64bit x86: NMI nesting still buggy?

On 04/30/2014 03:10 PM, Jiri Kosina wrote:
> On Tue, 29 Apr 2014, H. Peter Anvin wrote:
> 
>>> [2] 	"A special case can occur if an SMI handler nests inside an NMI 
>>> 	 handler and then another NMI occurs. During NMI interrupt 
>>> 	 handling, NMI interrupts are disabled, so normally NMI interrupts 
>>>  	 are serviced and completed with an IRET instruction one at a 
>>> 	 time. When the processor enters SMM while executing an NMI 
>>> 	 handler, the processor saves the SMRAM state save map but does 
>>> 	 not save the attribute to keep NMI interrupts disabled. 
>>> 	 Potentially, an NMI could be latched (while in SMM or upon exit) 
>>> 	 and serviced upon exit of SMM even though the previous NMI  
>>> 	 handler has still not completed."
>>
>> I believe [2] only applies if there is an IRET executing inside the SMM
>> handler, which should not normally be the case.  It might also have been
>> addressed since that was written, but I don't know.
> 
> Is there any chance that Intel would reveal what's behind this paragraph 
> and how likely it is to expect such BIOSes in the wild?
> 

I can ask internally and try to find out.  It  might very well be stale,
I don't know.

	-hpa


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