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Message-Id: <1399483554-8824-2-git-send-email-boris.brezillon@free-electrons.com>
Date: Wed, 7 May 2014 19:25:48 +0200
From: Boris BREZILLON <boris.brezillon@...e-electrons.com>
To: Emilio López <emilio@...pez.com.ar>,
Mike Turquette <mturquette@...aro.org>,
Samuel Ortiz <sameo@...ux.intel.com>,
Lee Jones <lee.jones@...aro.org>
Cc: Chen-Yu Tsai <wens@...e.org>,
Maxime Ripard <maxime.ripard@...e-electrons.com>,
Philipp Zabel <p.zabel@...gutronix.de>,
Shuge <shuge@...winnertech.com>, kevin@...winnertech.com,
Hans de Goede <hdegoede@...hat.com>,
Randy Dunlap <rdunlap@...radead.org>,
devicetree@...r.kernel.org, linux-doc@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
dev@...ux-sunxi.org,
Boris BREZILLON <boris.brezillon@...e-electrons.com>
Subject: [PATCH v2 1/7] reset: sunxi: document sunxi's reset controllers bindings
Add DT bindings documentation for sunxi's reset controllers.
Signed-off-by: Boris BREZILLON <boris.brezillon@...e-electrons.com>
---
.../bindings/reset/allwinner,sunxi-clock-reset.txt | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt
diff --git a/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt b/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt
new file mode 100644
index 0000000..c8f7757
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt
@@ -0,0 +1,21 @@
+Allwinner sunxi Peripheral Reset Controller
+===========================================
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+Required properties:
+- compatible: Should be one of the following:
+ "allwinner,sun6i-a31-ahb1-reset"
+ "allwinner,sun6i-a31-clock-reset"
+- reg: should be register base and length as documented in the
+ datasheet
+- #reset-cells: 1, see below
+
+example:
+
+ahb1_rst: reset@...202c0 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-ahb1-reset";
+ reg = <0x01c202c0 0xc>;
+};
--
1.8.3.2
--
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