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Message-Id: <1399504115-16257-3-git-send-email-b.galvani@gmail.com>
Date: Thu, 8 May 2014 01:08:34 +0200
From: Beniamino Galvani <b.galvani@...il.com>
To: Thierry Reding <thierry.reding@...il.com>
Cc: Heiko Stuebner <heiko@...ech.de>, linux-pwm@...r.kernel.org,
Rob Herring <robh+dt@...nel.org>,
Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Kumar Gala <galak@...eaurora.org>,
Randy Dunlap <rdunlap@...radead.org>,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
devicetree@...r.kernel.org, Beniamino Galvani <b.galvani@...il.com>
Subject: [PATCH 2/3] pwm: rockchip: document device tree bindings
This adds binding documentation for Rockchip SoC PWM driver.
Signed-off-by: Beniamino Galvani <b.galvani@...il.com>
---
.../devicetree/bindings/pwm/pwm-rockchip.txt | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/pwm-rockchip.txt
diff --git a/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt b/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt
new file mode 100644
index 0000000..35deba4
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt
@@ -0,0 +1,17 @@
+Rockchip PWM controller
+
+Required properties:
+ - compatible: should be "rockchip,rk2928-pwm"
+ - reg: physical base address and length of the controller's registers
+ - clocks: phandle and clock specifier of the PWM reference clock
+ - #pwm-cells: should be 2. See pwm.txt in this directory for a
+ description of the cell format
+
+Example:
+
+ pwm0: pwm@...30000 {
+ compatible = "rockchip,rk2928-pwm";
+ reg = <0x20030000 0x10>;
+ clocks = <&cru PCLK_PWM01>;
+ #pwm-cells = <2>;
+ };
--
1.7.10.4
--
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