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Message-ID: <20140511044526.GQ7047@lukather>
Date: Sun, 11 May 2014 06:45:26 +0200
From: Maxime Ripard <maxime.ripard@...e-electrons.com>
To: Matthias Brugger <matthias.bgg@...il.com>
Cc: linux-kernel@...r.kernel.org, robh+dt@...nel.org,
pawel.moll@....com, mark.rutland@....com,
ijc+devicetree@...lion.org.uk, galak@...eaurora.org,
rdunlap@...radead.org, linux@....linux.org.uk,
daniel.lezcano@...aro.org, tglx@...utronix.de,
thierry.reding@...il.com, florian.vaussard@...l.ch,
jic23@...nel.org, jason@...edaemon.net, andrew@...n.ch,
silvio.fricke@...il.com, heiko.stuebner@...com, olof@...om.net,
sebastian.hesselbarth@...il.com, sboyd@...eaurora.org,
gregory.clement@...e-electrons.com, arnd@...db.de,
robherring2@...il.com, marc.zyngier@....com,
devicetree@...r.kernel.org, linux-doc@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v2 1/4] clocksource: Add support for the Mediatek SoCs
On Sun, May 11, 2014 at 03:41:00AM +0200, Matthias Brugger wrote:
> This patch adds a clock source and clock event for the timer found
> on the Mediatek SoCs.
>
> The Mediatek General Porpose Timer block provides five 32 bit timers and
> one 64 bit timer.
>
> Two 32 bit timers are used:
> TIMER1: clock events supporting periodic and oneshot events
> TIMER2: clock source configured as a free running counter
>
> The General Porpose Timer block can be run with two clocks. A 13 MHz system
> clock and the RTC clock running at 32 KHz. This implementation uses the system
> clock.
>
> Signed-off-by: Matthias Brugger <matthias.bgg@...il.com>
> ---
> drivers/clocksource/Kconfig | 4 +
> drivers/clocksource/Makefile | 1 +
> drivers/clocksource/mtk_timer.c | 240 ++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 245 insertions(+)
> create mode 100644 drivers/clocksource/mtk_timer.c
>
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index 96918e1..1f73740 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -144,6 +144,10 @@ config VF_PIT_TIMER
> config SYS_SUPPORTS_SH_CMT
> bool
>
> +config MTK_TIMER
> + select CLKSRC_MMIO
> + bool
> +
> config SYS_SUPPORTS_SH_MTU2
> bool
>
> diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
> index 98cb6c5..619d302 100644
> --- a/drivers/clocksource/Makefile
> +++ b/drivers/clocksource/Makefile
> @@ -33,6 +33,7 @@ obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exynos_mct.o
> obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) += samsung_pwm_timer.o
> obj-$(CONFIG_VF_PIT_TIMER) += vf_pit_timer.o
> obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o
> +obj-$(CONFIG_MTK_TIMER) += mtk_timer.o
>
> obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
> obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o
> diff --git a/drivers/clocksource/mtk_timer.c b/drivers/clocksource/mtk_timer.c
> new file mode 100644
> index 0000000..796b888
> --- /dev/null
> +++ b/drivers/clocksource/mtk_timer.c
> @@ -0,0 +1,240 @@
> +/*
> + * Mediatek SoCs General-Purpose Timer handling.
> + *
> + * Copyright (C) 2014 Matthias Brugger
> + *
> + * Matthias Brugger <matthias.bgg@...il.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clockchips.h>
> +#include <linux/interrupt.h>
> +#include <linux/irq.h>
> +#include <linux/irqreturn.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +
> +#define GPT_IRQ_EN_REG 0x00
> +#define GPT_IRQ_ENABLE(val) BIT(val-1)
> +#define GPT_IRQ_ST_REG 0x04
> +#define GPT_IRQ_ACK_REG 0x08
> +#define GPT_IRQ_ACK(val) BIT(val-1)
> +
> +#define TIMER_CTRL_REG(val) (0x10 * val)
> +#define TIMER_CTRL_OP(val) (((val) & 0x3) << 4)
> +#define TIMER_CTRL_OP_ONESHOT (0)
> +#define TIMER_CTRL_OP_REPEAT (1)
> +#define TIMER_CTRL_OP_KEEPGO (2)
> +#define TIMER_CTRL_OP_FREERUN (3)
> +#define TIMER_CTRL_CLEAR (2)
> +#define TIMER_CTRL_ENABLE (1)
> +#define TIMER_CTRL_DISABLE (0)
> +
> +#define TIMER_CLK_REG(val) (0x04 + (0x10 * val))
> +#define TIMER_CLK_SRC(val) (((val) & 0x1) << 4)
> +#define TIMER_CLK_SRC_SYS13M (0)
> +#define TIMER_CLK_SRC_RTC32K (1)
> +#define TIMER_CLK_DIV1 (0x0)
> +#define TIMER_CLK_DIV2 (0x1)
> +#define TIMER_CLK_DIV3 (0x2)
> +#define TIMER_CLK_DIV4 (0x3)
> +#define TIMER_CLK_DIV5 (0x4)
> +#define TIMER_CLK_DIV6 (0x5)
> +#define TIMER_CLK_DIV7 (0x6)
> +#define TIMER_CLK_DIV8 (0x7)
> +#define TIMER_CLK_DIV9 (0x8)
> +#define TIMER_CLK_DIV10 (0x9)
> +#define TIMER_CLK_DIV11 (0xA)
> +#define TIMER_CLK_DIV12 (0xB)
> +#define TIMER_CLK_DIV13 (0xC)
> +#define TIMER_CLK_DIV16 (0xD)
> +#define TIMER_CLK_DIV32 (0xE)
> +#define TIMER_CLK_DIV64 (0xF)
> +
> +#define TIMER_CNT_REG(val) (0x08 + (0x10 * val))
> +#define TIMER_CMP_REG(val) (0x0C + (0x10 * val))
> +
> +#define GPT_CLK_EVT 1
> +#define GPT_CLK_SRC 2
> +
> +static void __iomem *gpt_base;
> +static u32 ticks_per_jiffy;
> +
> +static void mtk_clkevt_time_stop(u8 timer)
> +{
> + u32 val = readl(gpt_base + TIMER_CTRL_REG(timer));
> + writel(val & ~TIMER_CTRL_ENABLE, gpt_base + TIMER_CTRL_REG(timer));
> +}
> +
> +static void mtk_clkevt_time_setup(unsigned long delay, u8 timer)
> +{
> + writel(delay, gpt_base + TIMER_CMP_REG(timer));
> +}
> +
> +static void mtk_clkevt_time_start(bool periodic, u8 timer)
> +{
> + u32 val;
> +
> + /* Acknowledge interrupt */
> + writel(GPT_IRQ_ACK(timer), gpt_base + GPT_IRQ_ACK_REG);
> +
> + val = readl(gpt_base + TIMER_CTRL_REG(timer));
> +
> + /* Clear 2 bit timer operation mode field */
> + val &= ~TIMER_CTRL_OP(0x3);
> +
> + if (periodic)
> + val |= TIMER_CTRL_OP(TIMER_CTRL_OP_REPEAT);
> + else
> + val |= TIMER_CTRL_OP(TIMER_CTRL_OP_ONESHOT);
> +
> + writel(val | TIMER_CTRL_ENABLE | TIMER_CTRL_CLEAR,
> + gpt_base + TIMER_CTRL_REG(timer));
> +}
> +
> +static void mtk_clkevt_mode(enum clock_event_mode mode,
> + struct clock_event_device *clk)
> +{
> + mtk_clkevt_time_stop(GPT_CLK_EVT);
> +
> + switch (mode) {
> + case CLOCK_EVT_MODE_PERIODIC:
> + mtk_clkevt_time_setup(ticks_per_jiffy, GPT_CLK_EVT);
> + mtk_clkevt_time_start(true, GPT_CLK_EVT);
> + break;
> + case CLOCK_EVT_MODE_ONESHOT:
> + mtk_clkevt_time_start(false, GPT_CLK_EVT);
> + break;
> + case CLOCK_EVT_MODE_UNUSED:
> + case CLOCK_EVT_MODE_SHUTDOWN:
> + default:
> + /* No more interrupts will occur as source is disabled */
> + break;
> + }
> +}
> +
> +static int mtk_clkevt_next_event(unsigned long evt,
> + struct clock_event_device *unused)
> +{
> + mtk_clkevt_time_stop(GPT_CLK_EVT);
> + mtk_clkevt_time_setup(evt, GPT_CLK_EVT);
> + mtk_clkevt_time_start(false, GPT_CLK_EVT);
> +
> + return 0;
> +}
> +
> +static struct clock_event_device mtk_clockevent = {
> + .name = "mtk_tick",
> + .rating = 300,
> + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
> + .set_mode = mtk_clkevt_mode,
> + .set_next_event = mtk_clkevt_next_event,
> +};
> +
> +
> +static irqreturn_t mtk_timer_interrupt(int irq, void *dev_id)
> +{
> + struct clock_event_device *evt = dev_id;
> +
> + /* Acknowledge timer0 irq */
> + writel(GPT_IRQ_ACK(GPT_CLK_EVT), gpt_base + GPT_IRQ_ACK_REG);
> + evt->event_handler(evt);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static void mtk_timer_global_reset(void)
> +{
> + /* Disable all interrupts */
> + writel(0x0, gpt_base + GPT_IRQ_EN_REG);
> + /* Acknowledge all interrupts */
> + writel(0x3f, gpt_base + GPT_IRQ_ACK_REG);
> +}
> +
> +static void mtk_timer_reset(u8 timer)
> +{
> + writel(TIMER_CTRL_CLEAR | TIMER_CTRL_DISABLE,
> + gpt_base + TIMER_CTRL_REG(timer));
> + writel(0x0, gpt_base + TIMER_CMP_REG(timer));
> +}
> +
> +static void __init mtk_timer_init(struct device_node *node)
> +{
> + struct resource res;
> + unsigned long rate = 0;
> + struct clk *clk;
> + int ret, irq;
> + u32 val;
> +
> + if (of_address_to_resource(node, 0, &res))
> + panic("Failed to parse resource\n");
> +
> + if (!request_mem_region(res.start, resource_size(&res), "mtk-timer"))
> + panic("Registers are a busy IO resource");
> +
> + gpt_base = ioremap(res.start, resource_size(&res));
> + if (!gpt_base)
> + panic("Can't map registers");
> +
> + irq = irq_of_parse_and_map(node, 0);
> + if (irq <= 0)
> + panic("Can't parse IRQ");
> +
> + clk = of_clk_get(node, 0);
> + if (IS_ERR(clk))
> + panic("Can't get timer clock");
> +
> + clk_prepare_enable(clk);
> + rate = clk_get_rate(clk);
> +
> + mtk_timer_global_reset();
> +
> + /* Configure clock source */
> + mtk_timer_reset(GPT_CLK_SRC);
> +
> + writel(TIMER_CLK_SRC(TIMER_CLK_SRC_SYS13M) | TIMER_CLK_DIV1,
> + gpt_base + TIMER_CLK_REG(GPT_CLK_SRC));
> +
> + writel(TIMER_CTRL_OP(TIMER_CTRL_OP_FREERUN) | TIMER_CTRL_ENABLE,
> + gpt_base + TIMER_CTRL_REG(GPT_CLK_SRC));
> +
> + clocksource_mmio_init(gpt_base + TIMER_CNT_REG(GPT_CLK_SRC), node->name,
> + rate, 300, 32, clocksource_mmio_readl_up);
> +
> + ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
> +
> + /* Configure clock event */
> + mtk_timer_reset(GPT_CLK_EVT);
> +
> + writel(TIMER_CLK_SRC(TIMER_CLK_SRC_SYS13M) | TIMER_CLK_DIV1,
> + gpt_base + TIMER_CLK_REG(GPT_CLK_EVT));
> + writel(0, gpt_base + TIMER_CMP_REG(GPT_CLK_EVT));
> +
> + writel(TIMER_CTRL_OP(TIMER_CTRL_OP_REPEAT) | TIMER_CTRL_ENABLE,
> + gpt_base + TIMER_CTRL_REG(GPT_CLK_EVT));
> +
> + ret = request_irq(irq, mtk_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
> + "mtk_timer", &mtk_clockevent);
> + if (ret)
> + pr_warn("failed to setup irq %d\n", irq);
> +
> + /* Enable timer0 interrupt */
> + val = readl(gpt_base + GPT_IRQ_EN_REG);
> + writel(val | GPT_IRQ_ENABLE(GPT_CLK_EVT), gpt_base + GPT_IRQ_EN_REG);
> +
> + clockevents_config_and_register(&mtk_clockevent, rate, 0x3,
> + 0xffffffff);
You should also set the cpumask and irq fields in mtk_clockevent.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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