lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <537210BF.2050100@ti.com>
Date:	Tue, 13 May 2014 18:01:59 +0530
From:	Kishon Vijay Abraham I <kishon@...com>
To:	Arnd Bergmann <arnd@...db.de>, Jingoo Han <jg1.han@...sung.com>
CC:	"'Santosh Shilimkar'" <santosh.shilimkar@...com>,
	<devicetree@...r.kernel.org>, <linux-doc@...r.kernel.org>,
	<linux-kernel@...r.kernel.org>,
	<linux-arm-kernel@...ts.infradead.org>,
	<linux-omap@...r.kernel.org>, <linux-pci@...r.kernel.org>,
	<rogerq@...com>, <balajitk@...com>,
	"'Bjorn Helgaas'" <bhelgaas@...gle.com>,
	"'Marek Vasut'" <marex@...x.de>
Subject: Re: [PATCH 06/17] pci: host: pcie-designware: Use *base-mask* for
 configuring the iATU

Hi Arnd,

On Thursday 08 May 2014 02:48 PM, Arnd Bergmann wrote:
> On Thursday 08 May 2014 18:05:11 Jingoo Han wrote:
>> On Tuesday, May 06, 2014 10:59 PM, Arnd Bergmann wrote:
>>> On Tuesday 06 May 2014 19:03:52 Kishon Vijay Abraham I wrote:
>>>> In DRA7, the cpu sees 32bit address, but the pcie controller can see only 28bit
>>>> address. So whenever the cpu issues a read/write request, the 4 most
>>>> significant bits are used by L3 to determine the target controller.
>>>> For example, the cpu reserves 0x2000_0000 - 0x2FFF_FFFF for PCIe controller but
>>>> the PCIe controller will see only (0x000_0000 - 0xFFF_FFF). So for programming
>>>> the outbound translation window the *base* should be programmed as 0x000_0000.
>>>> Whenever we try to write to say 0x2000_0000, it will be translated to whatever
>>>> we have programmed in the translation window with base as 0x000_0000.
>>>>
>>>> Cc: Bjorn Helgaas <bhelgaas@...gle.com>
>>>> Cc: Marek Vasut <marex@...x.de>
>>>> Signed-off-by: Kishon Vijay Abraham I <kishon@...com>
>>>> Acked-by: Jingoo Han <jg1.han@...sung.com>
>>>> Acked-by: Mohit Kumar <mohit.kumar@...com>
>>>
>>> Sorry, but NAK.
>>>
>>> We have a standard 'dma-ranges' property to handle this, so use it.
>>>
>>> See the x-gene PCIe driver patches for an example. Please also talk
>>> to Santosh about it, as he is implementing generic support for
>>> parsing dma-ranges in platform devices at the moment.
>>
>> Hi Arnd,
>>
>> Do you mean the following patch?
>> http://www.spinics.net/lists/kernel/msg1737725.html
>>
> 
> That is the patch Santosh did for platform devices, which is related but not
> what I meant here. For the PCI inbound window setup, please have a look
> at https://lkml.org/lkml/2014/3/19/607

Do you think it can be used for *outbound* window setup too? The problem is the
*ranges* property defines both the pci address and cpu address which should
have been enough to program the ob translation window, but the hw is designed
so that the controller sees only the 28 bits. (The most significant 4 bits is
for the l3 to address the controller).

Thanks
Kishon
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ