linux-kernel - Re: [PATCH 03/17] phy: ti-pipe3: add external clock support for PCIe PHY

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Message-ID: <CAGo_u6qw1OomEw_ueb3x+xT+qZLAfGv7Se1K=o725aOoD3ankQ@mail.gmail.com>
Date:	Wed, 14 May 2014 10:34:09 -0500
From:	Nishanth Menon <nm@...com>
To:	Kishon Vijay Abraham I <kishon@...com>
Cc:	Roger Quadros <rogerq@...com>,
	dt list <devicetree@...r.kernel.org>,
	"linux-doc@...r.kernel.org" <linux-doc@...r.kernel.org>,
	lkml <linux-kernel@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	linux-omap <linux-omap@...r.kernel.org>,
	linux-pci@...r.kernel.org, Tero Kristo <t-kristo@...com>,
	Paul Walmsley <paul@...an.com>, Rajendra Nayak <rnayak@...com>,
	"Krishnamoorthy, Balaji T" <balajitk@...com>
Subject: Re: [PATCH 03/17] phy: ti-pipe3: add external clock support for PCIe PHY

On Wed, May 14, 2014 at 10:19 AM, Kishon Vijay Abraham I <kishon@...com> wrote:
> Hi Roger,
>
> On Wednesday 14 May 2014 06:46 PM, Roger Quadros wrote:
>> Hi Kishon,
>>
>> On 05/06/2014 04:33 PM, Kishon Vijay Abraham I wrote:
>>> APLL used by PCIE phy can either use external clock as input or the clock
>>> from DPLL. Added support for the APLL to use external clock as input here.
>>>
>>> Cc: Rajendra Nayak <rnayak@...com>
>>> Cc: Tero Kristo <t-kristo@...com>
>>> Cc: Paul Walmsley <paul@...an.com>
>>> Signed-off-by: Kishon Vijay Abraham I <kishon@...com>
>>> ---
>>>  Documentation/devicetree/bindings/phy/ti-phy.txt |    4 ++
>>>  drivers/phy/phy-ti-pipe3.c                       |   75 ++++++++++++++--------
>>>  2 files changed, 52 insertions(+), 27 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt b/Documentation/devicetree/bindings/phy/ti-phy.txt
>>> index bc9afb5..d50f8ee 100644
>>> --- a/Documentation/devicetree/bindings/phy/ti-phy.txt
>>> +++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
>>> @@ -76,6 +76,10 @@ Required properties:
>>>     * "dpll_ref_m2" - external dpll ref clk
>>>     * "phy-div" - divider for apll
>>>     * "div-clk" - apll clock
>>> +   * "apll_mux" - mux for pcie apll
>>> +   * "refclk_ext" - external reference clock for pcie apll
>>> + - ti,ext-clk: To specifiy if PCIE apll should use external clock. Applicable
>>> +   only to PCIE PHY.
>>
>> Instead of specifying both clock sources "dpll_ref_clock", "refclk_ext" and then specifying a 3rd control option "ti,ext-clk" to select one of the 2 sources, why can't the DT just supply one clock source, i.e. the one that is being used in the board instance? The driver should then just configure the clock rate that is needed at that node. Shouldn't the clock framework automatically take care of muxing and parent rates?
>
> Want the dt to have all the clocks used by the controller. "ti,ext-clk" should
> go in the board dt file (suggested by Nishanth).
> The point is at some point later if some one wants to change the clock source,
> it should be a simple enabling "ti,ext-clk" flag instead of finding the clock
> phandle etc..

Wonder if that is implicit by the presence of  "refclk_ext" in the
clocks provided?
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