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Message-ID: <CAKohpokoov4yr_oKW=Nv3gG1tfQMR2Wifr1=cD5s6MbvoFOUpQ@mail.gmail.com>
Date: Thu, 15 May 2014 11:42:44 +0530
From: Viresh Kumar <viresh.kumar@...aro.org>
To: Doug Anderson <dianders@...omium.org>
Cc: Nicolas Pitre <nicolas.pitre@...aro.org>,
Russell King - ARM Linux <linux@....linux.org.uk>,
"Rafael J. Wysocki" <rjw@...ysocki.net>,
Will Deacon <will.deacon@....com>,
John Stultz <john.stultz@...aro.org>,
David Riley <davidriley@...omium.org>,
"olof@...om.net" <olof@...om.net>,
Sonny Rao <sonnyrao@...omium.org>,
Santosh Shilimkar <santosh.shilimkar@...com>,
Shawn Guo <shawn.guo@...aro.org>,
Stephen Boyd <sboyd@...eaurora.org>,
Marc Zyngier <marc.zyngier@....com>,
Stephen Warren <swarren@...dia.com>,
Paul Gortmaker <paul.gortmaker@...driver.com>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] ARM: Don't ever downscale loops_per_jiffy in SMP systems#
On 14 May 2014 03:20, Doug Anderson <dianders@...omium.org> wrote:
> ...but then I found the true problem shows up when we transition
> between very low frequencies on exynos, like between 200MHz and
> 300MHz. While transitioning between frequencies the system
> temporarily bumps over to the "switcher" PLL running at 800MHz while
> waiting for the main PLL to stabilize. No CPUFREQ notification is
> sent for that. That means there's a period of time when we're running
> at 800MHz but loops_per_jiffy is calibrated at between 200MHz and
> 300MHz.
>
>
> I'm welcome to any suggestions for how to address this.
I have attempted to fix this in a generic way and sent an RFC patch for
this. I have cc'd only few people from this list which I thought would be
interested in cpufreq stuff, sorry if I missed anyone.
https://lkml.org/lkml/2014/5/15/40
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