linux-kernel - Re: [rfc]pwm: add xilinx pwm driver

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:	Thu, 15 May 2014 10:50:00 +0200
From:	Bart Tanghe <bart.tanghe@...masmore.be>
To:	Arnd Bergmann <arnd@...db.de>
CC:	thierry.reding@...il.com, michal.simek@...inx.com,
	robh+dt@...nel.org, pawel.moll@....com, mark.rutland@....com,
	ijc+devicetree@...lion.org.uk, galak@...eaurora.org,
	rob@...dley.net, grant.likely@...aro.org,
	linux-pwm@...r.kernel.org, devicetree@...r.kernel.org,
	linux-doc@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [rfc]pwm: add xilinx pwm driver

On 05/15/2014 09:23 AM, Arnd Bergmann wrote:
> On Wednesday 14 May 2014 13:26:13 Bart Tanghe wrote:
>> @@ -0,0 +1,20 @@
>> +Xilinx PWM controller
>> +
>> +Required properties:
>> +- compatible: should be "xlnx,pwm-xlnx"
>> +- add a clock source to the description
>> +
>> +Examples:
>> +
>> +               axi_timer_0: timer@...00000 {
>> +                       clock-frequency = <100000000>;
>> +                       clocks = <&clkc 15>;
>> +                       compatible = "xlnx,xlnx-pwm";
>> +                       reg = <0x42800000 0x10000>;
>> +                       xlnx,count-width = <0x20>;
>> +                       xlnx,gen0-assert = <0x1>;
>> +                       xlnx,gen1-assert = <0x1>;
>> +                       xlnx,one-timer-only = <0x0>;
>> +                       xlnx,trig0-assert = <0x1>;
>> +                       xlnx,trig1-assert = <0x1>;
>> +               } ;
>>
>
> It seems you are missing a mandatory "#pwm-cells" property.
> How is anybody supposed to use this?
>
> 	Arnd
>

I've added some additional information in the documentation



Xilinx PWM controller

This driver works together with the Xilinx Axi timer hardware core.
The core is available for the microblaze, powerpc and arm based Xilinx
platforms.

The axi timer core is implemented in the pl (programmable logic) of the
fpga. The amount is user defined. Each core has two timers and one pwm 
output.

After genereating the design and bitstream, you have to use the Xilinx 
device tree generator (git://git.xilinx.com/device-tree.git) to generate 
the dts file or the petalinux tools 
(http://www.xilinx.com/tools/petalinux-sdk.htm).

Within this dts file, you find the axi-timer and clock definitions.

		axi_timer_0: timer@...00000 {
			clock-frequency = <100000000>;
			compatible = "xlnx,axi-timer-2.0", "xlnx,xps-timer-1.00.a";
			reg = <0x42800000 0x10000>;
			xlnx,count-width = <0x20>;
			xlnx,gen0-assert = <0x1>;
			xlnx,gen1-assert = <0x1>;
			xlnx,one-timer-only = <0x0>;
			xlnx,trig0-assert = <0x1>;
			xlnx,trig1-assert = <0x1>;
		} ;

		...

ps7_slcr_0: ps7-slcr@...00000 {
compatible = "xlnx,ps7-slcr-1.00.a", "xlnx,zynqslcr";
reg = <0xf8000000 0x1000>;
clocks {
	#address-cells = <1>;
	#size-cells = <0>;
	clkc: clkc {
		#clock-cells = <1>;
		clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", 
"cpu_3or2x",
		"cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci",
		"lqspi", "smc", "pcap", "gem0", "gem1",
		"fclk0", "fclk1", "fclk2", "fclk3", "can0",
		"can1", "sdio0", "sdio1", "uart0", "uart1",
		"spi0", "spi1", "dma", "usb0_aper", "usb1_aper",
		"gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper",
		"spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper",
		"uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper",
		"swdt", "dbg_trc", "dbg_apb";
	compatible = "xlnx,ps7-clkc";
	fclk-enable = <0xf>;
	ps-clk-frequency = <33333333>;
	} ;
} ;
} ;

Some required properties should be changed
- compatible: should be "xlnx,pwm-xlnx"
- add the right clock source to the description - clocks = <&clkc 15>; 
fclk0 in this design
- add #pwm-cells = <1>;

Examples:

		axi_timer_0: timer@...00000 {
			clock-frequency = <100000000>;
			#pwm-cells = <1>;
			clocks = <&clkc 15>;
			compatible = "xlnx,xlnx-pwm";
			reg = <0x42800000 0x10000>;
			xlnx,count-width = <0x20>;
			xlnx,gen0-assert = <0x1>;
			xlnx,gen1-assert = <0x1>;
			xlnx,one-timer-only = <0x0>;
			xlnx,trig0-assert = <0x1>;
			xlnx,trig1-assert = <0x1>;
		} ;

Generate the dtb file and load it on the target platform.

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/