linux-kernel - RE: [PATCH v1 5/5] pci: keystone: add pcie driver based on designware core driver

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Message-ID: <3E54258959B69E4282D79E01AB1F32B704742133@DFLE11.ent.ti.com>
Date:	Fri, 16 May 2014 20:29:56 +0000
From:	"Karicheri, Muralidharan" <m-karicheri2@...com>
To:	Jason Gunthorpe <jgunthorpe@...idianresearch.com>
CC:	Arnd Bergmann <arnd@...db.de>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"Strashko, Grygorii" <grygorii.strashko@...com>,
	"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
	Jingoo Han <jg1.han@...sung.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"Shilimkar, Santosh" <santosh.shilimkar@...com>,
	Mohit Kumar <mohit.kumar@...com>,
	"Bjorn Helgaas" <bhelgaas@...gle.com>
Subject: RE: [PATCH v1 5/5] pci: keystone: add pcie driver based on
 designware core driver

>-----Original Message-----
>From: Jason Gunthorpe [mailto:jgunthorpe@...idianresearch.com]
>Sent: Thursday, May 15, 2014 4:52 PM
>To: Karicheri, Muralidharan
>Cc: Arnd Bergmann; linux-arm-kernel@...ts.infradead.org; Strashko, Grygorii; linux-
>pci@...r.kernel.org; Jingoo Han; linux-kernel@...r.kernel.org; Shilimkar, Santosh; Mohit
>Kumar; Bjorn Helgaas
>Subject: Re: [PATCH v1 5/5] pci: keystone: add pcie driver based on designware core
>driver
>
>On Thu, May 15, 2014 at 04:04:47PM -0400, Murali Karicheri wrote:
>
>> Jason What you mean by "The PCI core handles setting the maximum read
>> request size already" I see there is function pcie_write_mrrs() in the
>> drivers/pci/probe.c that reads the mps using pcie_get_mps() and then
>> set mrrs to mps. But this function is called only from
>> pcie_bus_configure_set() that is called by
>> pcie_bus_configure_settings()
>
>Right, that is the common code that correctly sets the MRRS that you should be using
>instead of quirks.
>
>> None of them gets called on ARM platform.
>
>Hmm, a cursory glance tells me the same as well.
>
>That seems to be the root problem here, ARM needs to do the PCIE setup just as much as
>any other arch.
>
>So, I would prefer to see you fix ARM common code to call
>pcie_bus_configure_settings() properly, that seems very simple and is obviously needed for
>any PCI-E host driver on ARM.
>

But pcie_bus_configure_settings just make sure the mrrs for a device is not greater than
the max payload size. But the quirk that I need is to limit the size of mrr to 256 as required
by the keystone PCI controller. So I still need to implement a quirk to enforce this limit.

In my reply to Arnd, I have agreed to move the quirk to keystone driver.

Murali
>Thoughts? Arnd? Bjorn?
>
>Jason
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