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Message-ID: <20140519112545.GD5027@krava.brq.redhat.com>
Date:	Mon, 19 May 2014 13:25:45 +0200
From:	Jiri Olsa <jolsa@...hat.com>
To:	Don Zickus <dzickus@...hat.com>
Cc:	Stephane Eranian <eranian@...gle.com>,
	Peter Zijlstra <peterz@...radead.org>,
	Arnaldo Carvalho de Melo <acme@...stprotocols.net>,
	LKML <linux-kernel@...r.kernel.org>,
	Namhyung Kim <namhyung@...il.com>,
	Andi Kleen <andi@...stfloor.org>
Subject: Re: [PATCH 6/6] perf: Add dcacheline sort

On Fri, May 16, 2014 at 12:24:41PM -0400, Don Zickus wrote:
> On Fri, May 16, 2014 at 06:02:43PM +0200, Stephane Eranian wrote:
> > On Fri, May 16, 2014 at 5:59 PM, Peter Zijlstra <peterz@...radead.org> wrote:
> > > On Fri, May 16, 2014 at 04:09:59PM +0200, Stephane Eranian wrote:
> > >> > +#define CACHE_LINESIZE       64
> > >> I had something similar to your patch here in my original series for
> > >> perf mem, but I never pushed it.
> > >> I think this is a useful feature to have.
> > >> However, I don't think you can hardcode the cache line size to 64.
> > >> This is generic
> > >> code. There may be architectures where the line size is different from 64.
> > >> So I think you should add an option to change the default line size or provide
> > >> an arch-specific definition.
> > >
> > > # cat /sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size
> > > 64
> > Excellent, then we should use that!
> 
> Would it make sense to create an accessory function that sets the size in
> util/cpumap.c and provides it as an inline from util/cpumap.h?

sounds good,

btw so far I'll take patches 1-4 (after getting changelog update)
and expecting v2 for 5,6 ;-)

thanks,
jirka
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