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Message-ID: <5080348.QmhgfQRxZW@wuerfel>
Date: Tue, 20 May 2014 12:08:44 +0200
From: Arnd Bergmann <arnd@...db.de>
To: Thierry Reding <thierry.reding@...il.com>
Cc: Dave Martin <Dave.Martin@....com>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
Rob Herring <robh+dt@...nel.org>,
Pawel Moll <Pawel.Moll@....com>,
Mark Rutland <Mark.Rutland@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Kumar Gala <galak@...eaurora.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-samsung-soc@...r.kernel.org"
<linux-samsung-soc@...r.kernel.org>,
Stephen Warren <swarren@...dotorg.org>,
Grant Grundler <grundler@...omium.org>,
Joerg Roedel <joro@...tes.org>,
Will Deacon <Will.Deacon@....com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Marc Zyngier <Marc.Zyngier@....com>,
"iommu@...ts.linux-foundation.org" <iommu@...ts.linux-foundation.org>,
"linux-tegra@...r.kernel.org" <linux-tegra@...r.kernel.org>,
Cho KyongHo <pullip.cho@...sung.com>
Subject: Re: [PATCH] devicetree: Add generic IOMMU device tree bindings
On Monday 19 May 2014 22:32:33 Thierry Reding wrote:
> On Mon, May 19, 2014 at 06:22:31PM +0100, Dave Martin wrote:
> > On Mon, May 19, 2014 at 01:53:37PM +0100, Thierry Reding wrote:
> [...]
> > > My understanding here is mostly based on the OpenFirmware working group
> > > proposal for the dma-ranges property[0]. I'll give another example to
> > > try and clarify how I had imagined this to work:
> > >
> > > / {
> > > #address-cells = <2>;
> > > #size-cells = <2>;
> > >
> > > iommu {
> > > /*
> > > * This is somewhat unusual (or maybe not) in that we
> > > * need 2 cells to represent the size of an address
> > > * space that is 32 bits long.
> > > */
> > > #address-cells = <1>;
> > > #size-cells = <2>;
> > >
> > > #iommu-cells = <1>;
> > > };
> > >
> > > master {
> > > iommus = <&/iommu 42>;
> >
> > Comparing this with the other discussion thread, we have a similar
> > concept here, in that the iommu is made a logical parent, however...
> >
> > Firstly, there's an implicit assumption here that the only kind of
> > thing the master could possibly be connected to is an IOMMU, with
> > no non-trivial interconnect in between. I'm not sure this is going
> > to scale to complex SoCs.
>
> Here we go again. We're now in the very same bad spot that we've been in
> so many times before. There are at least two SoCs that we know do not
> require anything fancy, yet we're blocking adding support for those use
> cases because we think that at some point some IOMMU may require more
> than that. But at the same time it seems like we don't have enough data
> about what exactly that is, so we keep speculating. At this rate we're
> making it impossible to get a reasonable feature set supported upstream.
>
> That's very frustrating.
I agree. While I just commented that I want to think through how this
would look for other IOMMUs, the generic case of all masters that Dave
wants is going overboard with the complexity and we'd be better off
deferring this to whenever someone needs it, which I assume is never.
> > If a range of Stream IDs may be issued (especially from something like
> > a PCIe RC where the stream ID may be a many-bit value), describing
> > the IDs individually may be impractical.
>
> The IOMMU specifier is completely specific to the IOMMU. If an IOMMU has
> a need to represent the stream IDs as a range there's nothing keeping it
> from defining the specifier accordingly.
If we make the IOMMU address space look like the PCI address space, we
can have a simple representation for this in DT. For the code, I assume
that we will always have to treat PCI and platform devices differently.
Arnd
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