[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <537CE141.6010500@codeaurora.org>
Date: Wed, 21 May 2014 10:24:17 -0700
From: Stephen Boyd <sboyd@...eaurora.org>
To: Georgi Djakov <gdjakov@...sol.com>
CC: linux@....linux.org.uk, robh+dt@...nel.org, pawel.moll@....com,
mark.rutland@....com, ijc+devicetree@...lion.org.uk,
galak@...eaurora.org, rvaswani@...eaurora.org,
davidb@...eaurora.org, linux-arm-kernel@...ts.infradead.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-msm@...r.kernel.org
Subject: Re: [PATCH v1 1/4] ARM: dts: qcom: Add APQ8084 SoC support
On 05/21/14 07:57, Georgi Djakov wrote:
> +
> + L2: l2-cache {
> + compatible = "qcom,arch-cache";
> + cache-level = <2>;
> + interrupts = <0 2 0x4>;
Let's leave out interrupts until the binding is accepted.
> + qcom,saw = <&saw_l2>;
> + };
> + };
> +
> + cpu-pmu {
> + compatible = "qcom,krait-pmu";
> + interrupts = <1 7 0xf04>;
> + };
> +
> + soc: soc {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + compatible = "simple-bus";
> +
> + intc: interrupt-controller@...00000 {
> + compatible = "qcom,msm-qgic2";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + reg = <0xf9000000 0x1000>,
> + <0xf9002000 0x1000>;
> + };
> +
> + timer {
> + compatible = "arm,armv7-timer";
> + interrupts = <1 2 0xf08>,
> + <1 3 0xf08>,
> + <1 4 0xf08>,
> + <1 1 0xf08>;
> + clock-frequency = <19200000>;
> + };
Please move this timer node out of the soc container below the pmu.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Powered by blists - more mailing lists