linux-kernel - [Patch v6 2/7] clock: keystone-pllctrl: add bindings for keystone pll controller

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Message-ID: <1400777062-19276-3-git-send-email-ivan.khoronzhuk@ti.com>
Date:	Thu, 22 May 2014 19:44:17 +0300
From:	Ivan Khoronzhuk <ivan.khoronzhuk@...com>
To:	<dbaryshkov@...il.com>, <dwmw2@...radead.org>,
	<lee.jones@...aro.org>, <santosh.shilimkar@...com>,
	<arnd@...db.de>, <robh+dt@...nel.org>, <pawel.moll@....com>,
	<mark.rutland@....com>, <ijc+devicetree@...lion.org.uk>,
	<galak@...eaurora.org>, <grant.likely@...aro.org>
CC:	<rdunlap@...radead.org>, <linux@....linux.org.uk>,
	<grygorii.strashko@...com>, <olof@...om.net>, <w-kwok2@...com>,
	<sboyd@...eaurora.org>, <devicetree@...r.kernel.org>,
	<linux-doc@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
	<linux-arm-kernel@...ts.infradead.org>, <m-karicheri2@...com>,
	<sergei.shtylyov@...entembedded.com>,
	Ivan Khoronzhuk <ivan.khoronzhuk@...com>
Subject: [Patch v6 2/7] clock: keystone-pllctrl: add bindings for keystone pll controller

The main pll controller used to drive theC66x CorePacs, the switch fabric,
and a majority of the peripheral clocks (all but the ARM CorePacs, DDR3 and
the NETCP modules) requires a PLL Controller to manage the various clock
divisions, gating, and synchronization.

Reviewed-by: Arnd Bergmann <arnd@...db.de>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@...com>
---
 .../bindings/clock/ti-keystone-pllctrl.txt           | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/ti-keystone-pllctrl.txt

diff --git a/Documentation/devicetree/bindings/clock/ti-keystone-pllctrl.txt b/Documentation/devicetree/bindings/clock/ti-keystone-pllctrl.txt
new file mode 100644
index 0000000..3e6a81e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti-keystone-pllctrl.txt
@@ -0,0 +1,20 @@
+* Device tree bindings for Texas Instruments keystone pll controller
+
+The main pll controller used to drive theC66x CorePacs, the switch fabric,
+and a majority of the peripheral clocks (all but the ARM CorePacs, DDR3 and
+the NETCP modules) requires a PLL Controller to manage the various clock
+divisions, gating, and synchronization.
+
+Required properties:
+
+- compatible:		"ti,keystone-pllctrl", "syscon"
+
+- reg:			contains offset/length value for pll controller
+			registers space.
+
+Example:
+
+pllctrl: pll-controller@...2310000 {
+	compatible = "ti,keystone-pllctrl", "syscon";
+	reg = <0x02310000 0x200>;
+};
-- 
1.8.3.2

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