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Message-ID: <86bnuor706.fsf@void.printf.net>
Date: Fri, 23 May 2014 13:53:29 +0100
From: Chris Ball <chris@...ntf.net>
To: Ulf Hansson <ulf.hansson@...aro.org>
Cc: Andrew Bresticker <abrestic@...omium.org>,
Stephen Warren <swarren@...dotorg.org>,
Thierry Reding <thierry.reding@...il.com>,
linux-mmc <linux-mmc@...r.kernel.org>,
"linux-tegra\@vger.kernel.org" <linux-tegra@...r.kernel.org>,
"linux-kernel\@vger.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-arm-kernel\@lists.infradead.org"
<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v3 2/2] mmc: tegra: fix reporting of base clock frequency
Hi,
On Fri, May 23 2014, Ulf Hansson wrote:
> On 22 May 2014 17:55, Andrew Bresticker <abrestic@...omium.org> wrote:
>> Tegra SDHCI controllers, by default, report a base clock frequency
>> of 208Mhz in SDHCI_CAPABILTIES which may or may not be equal to the
>> actual base clock frequency. This is because the clock rate is
>> configured by the clock controller, which is external to the SD/MMC
>> controller. Since the SD/MMC controller has no knowledge of how this
>> clock is configured, it will simply report the maximum frequency.
>> While the reported value can be overridden by setting BASE_CLK_FREQ in
>> VENDOR_CLOCK_CTRL on Tegra30 and later SoCs, just set CAP_CLOCK_BASE_BROKEN
>> and supply sdhci_pltfm_clk_get_max_clock(), which simply does a
>> clk_get_rate(), as the get_max_clock() callback.
>>
>> Signed-off-by: Andrew Bresticker <abrestic@...omium.org>
>> Tested-by: Stephen Warren <swarren@...dia.com>
>> Acked-by: Stephen Warren <swarren@...dia.com>
>
> Thanks Andrew!
>
> Signed-off-by: Ulf Hansson <ulf.hansson@...aro.org>
>
> Chris, can you pick this up?
Thanks, pushed to mmc-next for 3.16.
- Chris.
--
Chris Ball <http://printf.net/>
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