linux-kernel - Re: [Patch V3 19/37] x86, irq: introduce mechanisms to support dynamically allocate IRQ for IOAPIC

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Message-ID: <alpine.DEB.2.02.1405281159030.21720@ionos.tec.linutronix.de>
Date:	Wed, 28 May 2014 12:07:50 +0200 (CEST)
From:	Thomas Gleixner <tglx@...utronix.de>
To:	Sebastian Andrzej Siewior <bigeasy@...utronix.de>
cc:	Jiang Liu <jiang.liu@...ux.intel.com>,
	Benjamin Herrenschmidt <benh@...nel.crashing.org>,
	Grant Likely <grant.likely@...aro.org>,
	Ingo Molnar <mingo@...hat.com>,
	"H. Peter Anvin" <hpa@...or.com>,
	"Rafael J. Wysocki" <rjw@...ysocki.net>,
	Bjorn Helgaas <bhelgaas@...gle.com>,
	Randy Dunlap <rdunlap@...radead.org>,
	Yinghai Lu <yinghai@...nel.org>, x86@...nel.org,
	Len Brown <len.brown@...el.com>, Pavel Machek <pavel@....cz>,
	Konrad Rzeszutek Wilk <konrad.wilk@...cle.com>,
	Andrew Morton <akpm@...ux-foundation.org>,
	Tony Luck <tony.luck@...el.com>,
	Joerg Roedel <joro@...tes.org>,
	Paul Gortmaker <paul.gortmaker@...driver.com>,
	Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
	linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
	linux-acpi@...r.kernel.org, Ingo Molnar <mingo@...nel.org>,
	linux-pm@...r.kernel.org
Subject: Re: [Patch V3 19/37] x86, irq: introduce mechanisms to support
 dynamically allocate IRQ for IOAPIC

On Wed, 28 May 2014, Sebastian Andrzej Siewior wrote:
> On 05/27/2014 09:58 PM, Thomas Gleixner wrote:
> > ce4100 is an oddball though. The ioapic is registered way before the
> > interrupt subsystem is initialized and I have a hard time to
> > understand that comment:
> > 
> >         /* We can't set this earlier, because we need to calibrate the timer */
> >         legacy_pic = &null_legacy_pic;
> > 
> > The timer calibration happens after the interrupts are set up. I
> > assume it's check_timer() which wants that, but we know exactly how
> > the ce4100 works, so we might be able to avoid that whole "testing"
> > stuff. Sebastian, any input on this?
> 
> According to my memory there was some PIC init we need but I don't
> recall the details. However, booting the system with "legacy_pic =
> &null_legacy_pic;" in x86_ce4100_early_setup() gives me this:
> 
> [    0.001000] Enabling APIC mode:  Flat.  Using 2 I/O APICs
> [    0.001000] leaving PIC mode, enabling APIC mode.
> [    0.001000] enabled ExtINT on CPU#0
> [    0.001000] ENABLING IO-APIC IRQs
> [    0.001000] Setting 1 in the phys_id_present_map
> [    0.001000] ...changing IO-APIC physical APIC ID to 1 ... ok.
> [    0.001000] Setting 2 in the phys_id_present_map
> [    0.001000] ...changing IO-APIC physical APIC ID to 2 ... ok.
> [    0.001000] smpboot: CPU0: Intel(R) Atom(TM) CPU CE4150   @ 1.20GHz
> (fam: 06, model: 1c, stepping: 0a)
> [    0.001000] Using local APIC timer interrupts.
> [    0.001000] calibrating APIC timer ...
> 
> and we stand still. With the assignment as it is now:
> 
> [    0.001000] Enabling APIC mode:  Flat.  Using 2 I/O APICs
> [    0.001000] leaving PIC mode, enabling APIC mode.
> [    0.001000] enabled ExtINT on CPU#0
> [    0.002312] ENABLING IO-APIC IRQs
> [    0.003009] Setting 1 in the phys_id_present_map
> [    0.004007] ...changing IO-APIC physical APIC ID to 1 ... ok.
> [    0.005533] Setting 2 in the phys_id_present_map
> [    0.006006] ...changing IO-APIC physical APIC ID to 2 ... ok.
> [    0.008373] ..TIMER: vector=0x30 apic1=-1 pin1=-1 apic2=-1 pin2=-1
> [    0.009000] ...trying to set up timer as Virtual Wire IRQ...
> [    0.019490] ..... works.

Right, so it needs the setup of irq 0 and that only happens when the
legacy_pic->nr_legacy_irqs > 0.

Do you remember, why we switch to the null_pic later on?

Thanks,

	tglx


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