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Message-ID: <20140528165144.GK29957@tassilo.jf.intel.com>
Date: Wed, 28 May 2014 09:51:44 -0700
From: Andi Kleen <ak@...ux.intel.com>
To: Stephane Eranian <eranian@...gle.com>
Cc: Peter Zijlstra <peterz@...radead.org>,
"Yan, Zheng" <zheng.z.yan@...el.com>,
LKML <linux-kernel@...r.kernel.org>,
"mingo@...e.hu" <mingo@...e.hu>
Subject: Re: [RFC PATCH 6/7] perf, x86: large PEBS interrupt threshold
> The only part I don't quite follow here is this:
> if (__test_and_set_bit(bit, (unsigned long *)&status))
> continue;
>
> Which seems to indicate the code is making sure each counter is
> processed only once. But it can only be processed once, if you have
> only one record. And if you have multiple, you want to be able to
> handle the same counter multiple times, at least once perf PEBS
> record. So I am a bit confused about this test.
Each PEBS record is only for a single counter overflow. So it
always should only be a single perf event.
-Andi
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