linux-kernel - Re: [RFC PATCH 6/7] perf, x86: large PEBS interrupt threshold

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Message-ID: <20140528171243.GL29957@tassilo.jf.intel.com>
Date:	Wed, 28 May 2014 10:12:43 -0700
From:	Andi Kleen <ak@...ux.intel.com>
To:	Stephane Eranian <eranian@...gle.com>
Cc:	Peter Zijlstra <peterz@...radead.org>,
	"Yan, Zheng" <zheng.z.yan@...el.com>,
	LKML <linux-kernel@...r.kernel.org>,
	"mingo@...e.hu" <mingo@...e.hu>
Subject: Re: [RFC PATCH 6/7] perf, x86: large PEBS interrupt threshold

> So, you're telling me this is a sanity check. That p->status can
> only have one bit set. Somehow that's not how I recall it working.

It can have multiple bits set. We don't know for sure for which
it is, but we should only deliver it for one anyways.

> The point is that a single PEBS record is enough for multiple
> events when the overflows occur simultaneously because they
> all get the same machine state which is correct.  A single entry
> also saves space in the buffer.

The CPU will generate multiple PEBS records in this case.
So if we delivered it for all you would overcount by factor 4x

[Again this is a very unlikely situation. Normally counters
are not in lock step]

-Andi

-- 
ak@...ux.intel.com -- Speaking for myself only
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