lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:	Thu, 29 May 2014 21:24:07 +0200
From:	Arnd Bergmann <arnd@...db.de>
To:	Santosh Shilimkar <santosh.shilimkar@...com>
Cc:	Linus Walleij <linus.walleij@...aro.org>,
	Grant Likely <grant.likely@...aro.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	Grygorii Strashko <grygorii.strashko@...com>,
	Russell King <linux@....linux.org.uk>,
	Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
	Rob Herring <robh+dt@...nel.org>,
	Catalin Marinas <catalin.marinas@....com>,
	Olof Johansson <olof@...om.net>
Subject: Re: [PATCH v3 4/7] of: configure the platform device dma parameters

On Thursday 29 May 2014 10:08:10 Santosh Shilimkar wrote:
> On Thursday 29 May 2014 10:01 AM, Linus Walleij wrote:
> > On Wed, May 28, 2014 at 4:04 PM, Santosh Shilimkar
> > <santosh.shilimkar@...com> wrote:
> >> On Wednesday 28 May 2014 09:32 AM, Linus Walleij wrote:
> > 
> >>>> I suspect what you want is
> >>>>
> >>>>         dma-ranges = <0x80000000 0 0x80000000>;
> >>>>
> >>>> to translate dma_addr_t 0x80000000-0xffffffff to phys_addr_t 0x0-0x7fffffff
> >>>> rather than phys_addr_t 0x800000000-0x87fffffff.
> >>>
> >> Interesting. Where does the ROM address space resides on integrator then considering
> >> address 0 is used for DMA.
> > 
> > The ROM is at physical address 0x20000000, don't ask me
> > why 
> > 
> > The RAM is typically at 0x00000000-0x0fffffff, on up to four parallell
> > tiles, i.e. up to four completely independent CPUs are booted off the
> > same ROM and using a set of shared peripherals.
> > 
> The reason I asked the question because most of the ARM SOC I came across
> aren't using the RAM phys address 0 and thought was because of boot architecture
> with ROM occupying that address with reset vector starting at address 0.
> 
> That was one of the main reason we had description on max_*pfn on ARM w.r.t
> to other acrhes.
> 
> Will corner ARM guys to understand bit more about it in some conference 

If this is anything like the versatile express, the reason it works is probably
because there is another microcontroller in the system that does the bootstrap
and is able to load code into RAM before turning on the main CPU.

	Arnd
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ