linux-kernel - Re: [PATCH v4 2/3] mfd: intel_soc

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Message-ID: <20140529114921.GK1954@lee--X1>
Date:	Thu, 29 May 2014 12:49:21 +0100
From:	Lee Jones <lee.jones@...aro.org>
To:	"Zhu, Lejun" <lejun.zhu@...ux.intel.com>
Cc:	broonie@...nel.org, sameo@...ux.intel.com,
	linux-kernel@...r.kernel.org, jacob.jun.pan@...ux.intel.com,
	bin.yang@...el.com
Subject: Re: [PATCH v4 2/3] mfd: intel_soc_pmic: Crystal Cove support

On Thu, 29 May 2014, Zhu, Lejun wrote:

> This patch provides chip-specific support for Crystal Cove. Crystal
> Cove is the PMIC in Baytrail-T platform.
> 
> Signed-off-by: Yang, Bin <bin.yang@...el.com>
> Signed-off-by: Zhu, Lejun <lejun.zhu@...ux.intel.com>
> ---
> v2:
> - Add regmap_config for Crystal Cove.
> v3:
> - Convert IRQ config to regmap_irq_chip.
> v4:
> - Cleanup include files.
> - Remove useless init() function.
> - Remove useless .label and .init from struct intel_soc_pmic_config.
> - Fix various coding style issues.
> ---
>  drivers/mfd/intel_soc_pmic_crc.c | 160 +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 160 insertions(+)
>  create mode 100644 drivers/mfd/intel_soc_pmic_crc.c
> 
> diff --git a/drivers/mfd/intel_soc_pmic_crc.c b/drivers/mfd/intel_soc_pmic_crc.c
> new file mode 100644
> index 0000000..43dbfcd
> --- /dev/null
> +++ b/drivers/mfd/intel_soc_pmic_crc.c
> @@ -0,0 +1,160 @@
> +/*
> + * intel_soc_pmic_crc.c - Device access for Crystal Cove PMIC
> + *
> + * Copyright (C) 2013, 2014 Intel Corporation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License version
> + * 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * Author: Yang, Bin <bin.yang@...el.com>
> + * Author: Zhu, Lejun <lejun.zhu@...ux.intel.com>
> + */
> +
> +#include <linux/mfd/core.h>
> +#include <linux/interrupt.h>
> +#include <linux/regmap.h>
> +#include <linux/mfd/intel_soc_pmic.h>
> +#include "intel_soc_pmic_core.h"
> +
> +#define CRYSTAL_COVE_MAX_REGISTER	0xC6
> +
> +#define REG_IRQLVL1			0x02
> +#define REG_MIRQLVL1			0x0E
> +
> +enum crystal_cove_irq {
> +	PWRSRC_IRQ = 0,
> +	THRM_IRQ,
> +	BCU_IRQ,
> +	ADC_IRQ,
> +	CHGR_IRQ,
> +	GPIO_IRQ,
> +	VHDMIOCP_IRQ
> +};

I can't help thinking that these should be nice clear #defines

#define CRYSTAL_COVE_IRQ_PWSRC 		0
...
#define CRYSTAL_COVE_IRQ_VHDMIOCP	6

[...]

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
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