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Message-ID: <CACRpkdZk9hFUZCoWci15EGFsJ7gOWNyFH13gJjHB9EcQT4ONRQ@mail.gmail.com>
Date:	Thu, 29 May 2014 17:22:05 +0200
From:	Linus Walleij <linus.walleij@...aro.org>
To:	Grygorii Strashko <grygorii.strashko@...com>
Cc:	Mika Westerberg <mika.westerberg@...ux.intel.com>,
	Alexandre Courbot <gnurou@...il.com>,
	"Zhu, Lejun" <lejun.zhu@...ux.intel.com>,
	Mathias Nyman <mathias.nyman@...ux.intel.com>,
	"linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
	jacob.jun.pan@...ux.intel.com, bin.yang@...el.com
Subject: Re: [PATCH v4] gpio: Add support for Intel SoC PMIC (Crystal Cove)

On Thu, May 29, 2014 at 6:03 PM, Grygorii Strashko
<grygorii.strashko@...com> wrote:

> Also, I'd like to note that GPIO IRQs can be accessible not only
> when GPIO chips is added, but also when IRQ domain is registered
> (at least it's valid for DT cases). In these cases gpiod_to_irq()
> might be not used at all.

Yes. We concluded some time back that gpio_chip:s and
irq_chip:s are orthogonal abstractions: you should be able
to use one of them without paying any respect to the other.

We only added the ability to flag GPIO lines as used for
IRQs so they would not be set to output by mistake...
(Straightening up the semantics.)

The only real semantic dependence that really makes sense
is .to_irq() which leads to this semantic registration ordering.

Yours,
Linus Walleij
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