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Message-ID: <20140602104405.GB13573@leverpostej>
Date:	Mon, 2 Jun 2014 11:44:05 +0100
From:	Mark Rutland <mark.rutland@....com>
To:	Antoine Ténart 
	<antoine.tenart@...e-electrons.com>
Cc:	"sebastian.hesselbarth@...il.com" <sebastian.hesselbarth@...il.com>,
	"alexandre.belloni@...e-electrons.com" 
	<alexandre.belloni@...e-electrons.com>,
	"thomas.petazzoni@...e-electrons.com" 
	<thomas.petazzoni@...e-electrons.com>,
	"zmxu@...vell.com" <zmxu@...vell.com>,
	"jszhang@...vell.com" <jszhang@...vell.com>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 2/5] Documentation: bindings: document the Marvell Berlin
 enable-method

On Mon, Jun 02, 2014 at 10:21:03AM +0100, Antoine Ténart wrote:
> The SMP support for Marvell Berlin SoCs introduce a new enable-method.
> Document it.
> 
> Signed-off-by: Antoine Ténart <antoine.tenart@...e-electrons.com>
> ---
>  Documentation/devicetree/bindings/arm/cpus.txt | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> index 333f4aea3029..50ec9ae6de28 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> @@ -185,6 +185,7 @@ nodes to be present and contain the properties described below.
>  			    "qcom,gcc-msm8660"
>  			    "qcom,kpss-acc-v1"
>  			    "qcom,kpss-acc-v2"
> +			    "marvell,berlin-smp"

And what does this mean?

The existing bindings are ambiguous enough. It would be nice to have a
proper document describing the method, as Alex Elder is trying to sort
out for the existing bindings.

Cheers,
Mark.
--
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