linux-kernel - Re: [PATCH v2] introduce atomic_pointer to fix a race condition in cancelable mcs spinlocks

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Date:	Mon, 02 Jun 2014 13:25:29 -0400
From:	Waiman Long <waiman.long@...com>
To:	Jason Low <jason.low2@...com>
CC:	Mikulas Patocka <mpatocka@...hat.com>,
	Linus Torvalds <torvalds@...ux-foundation.org>,
	Peter Zijlstra <peterz@...radead.org>, jejb@...isc-linux.org,
	deller@....de, John David Anglin <dave.anglin@...l.net>,
	linux-parisc@...r.kernel.org, linux-kernel@...r.kernel.org,
	paulmck@...ux.vnet.ibm.com, chegu_vinod@...com, tglx@...utronix.de,
	riel@...hat.com, akpm@...ux-foundation.org, davidlohr@...com,
	hpa@...or.com, andi@...stfloor.org, aswin@...com,
	scott.norton@...com
Subject: Re: [PATCH v2] introduce atomic_pointer to fix a race condition in
 cancelable mcs spinlocks

On 06/02/2014 12:50 PM, Jason Low wrote:
> On Mon, 2014-06-02 at 12:00 -0400, Mikulas Patocka wrote:
>> If you write to some variable with ACCESS_ONCE and use cmpxchg or xchg at
>> the same time, you break it. ACCESS_ONCE doesn't take the hashed spinlock,
>> so, in this case, cmpxchg or xchg isn't really atomic at all.
> So if the problem is using ACCESS_ONCE writes with cmpxchg and xchg at
> the same time, would the below change address this problem?
>
> -----
> diff --git a/kernel/locking/mcs_spinlock.c b/kernel/locking/mcs_spinlock.c
> index 838dc9e..8396721 100644
> --- a/kernel/locking/mcs_spinlock.c
> +++ b/kernel/locking/mcs_spinlock.c
> @@ -71,7 +71,7 @@ bool osq_lock(struct optimistic_spin_queue **lock)
>   	if (likely(prev == NULL))
>   		return true;
>
> -	ACCESS_ONCE(prev->next) = node;
> +	xchg(&prev->next, node);
>
>   	/*
>   	 * Normally @prev is untouchable after the above store; because at that
> @@ -144,7 +144,7 @@ unqueue:
>   	 */
>
>   	ACCESS_ONCE(next->prev) = prev;
> -	ACCESS_ONCE(prev->next) = next;
> +	xchg(&prev->next, next);
>
>   	return false;
>   }
>
>

Doing an xchg is a very expensive operation compared with ACCESS_ONCE. I 
will not suggest doing that to make it right for PA-RISC at the expense 
of performance in other architectures.

-Longman
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