linux-kernel - [tip:perf/core] perf/ARM: Use common PMU interrupt disabled code

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Date:	Thu, 5 Jun 2014 07:38:33 -0700
From:	tip-bot for Vince Weaver <tipbot@...or.com>
To:	linux-tip-commits@...r.kernel.org
Cc:	linux-kernel@...r.kernel.org, paulus@...ba.org,
	grant.likely@...aro.org, hpa@...or.com, mingo@...nel.org,
	torvalds@...ux-foundation.org, will.deacon@....com,
	peterz@...radead.org, acme@...nel.org, vincent.weaver@...ne.edu,
	linux@....linux.org.uk, robh+dt@...nel.org, tglx@...utronix.de
Subject: [tip:perf/core] perf/ARM: Use common PMU interrupt disabled code

Commit-ID:  edcb4d3c36a6429caa03ddfeab4cbb153c7002b2
Gitweb:     http://git.kernel.org/tip/edcb4d3c36a6429caa03ddfeab4cbb153c7002b2
Author:     Vince Weaver <vincent.weaver@...ne.edu>
AuthorDate: Fri, 16 May 2014 17:15:49 -0400
Committer:  Ingo Molnar <mingo@...nel.org>
CommitDate: Thu, 5 Jun 2014 12:30:00 +0200

perf/ARM: Use common PMU interrupt disabled code

Make the ARM perf code use the new common PMU interrupt disabled code.

This allows perf to work on ARM machines without a working PMU
interrupt (for example, raspberry pi).

Acked-by: Will Deacon <will.deacon@....com>
Signed-off-by: Vince Weaver <vincent.weaver@...ne.edu>
[peterz: applied changes suggested by Will]
Signed-off-by: Peter Zijlstra <peterz@...radead.org>
Cc: Arnaldo Carvalho de Melo <acme@...nel.org>
Cc: Grant Likely <grant.likely@...aro.org>
Cc: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: Paul Mackerras <paulus@...ba.org>
Cc: Rob Herring <robh+dt@...nel.org>
Cc: Russell King <linux@....linux.org.uk>
Cc: Will Deacon <will.deacon@....com>
Cc: devicetree@...r.kernel.org
Cc: linux-arm-kernel@...ts.infradead.org
Cc: linux-kernel@...r.kernel.org
Link: http://lkml.kernel.org/r/alpine.DEB.2.10.1405161712190.11099@vincent-weaver-1.umelst.maine.edu
[ Small readability tweaks to the code. ]
Signed-off-by: Ingo Molnar <mingo@...nel.org>

Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
 arch/arm/kernel/perf_event.c     | 2 +-
 arch/arm/kernel/perf_event_cpu.c | 8 ++++++--
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index a6bc431..4238bcb 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -410,7 +410,7 @@ __hw_perf_event_init(struct perf_event *event)
 	 */
 	hwc->config_base	    |= (unsigned long)mapping;
 
-	if (!hwc->sample_period) {
+	if (!is_sampling_event(event)) {
 		/*
 		 * For non-sampling runs, limit the sample_period to half
 		 * of the counter width. That way, the new counter value
diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c
index 51798d7..bbdbffd 100644
--- a/arch/arm/kernel/perf_event_cpu.c
+++ b/arch/arm/kernel/perf_event_cpu.c
@@ -126,8 +126,8 @@ static int cpu_pmu_request_irq(struct arm_pmu *cpu_pmu, irq_handler_t handler)
 
 	irqs = min(pmu_device->num_resources, num_possible_cpus());
 	if (irqs < 1) {
-		pr_err("no irqs for PMUs defined\n");
-		return -ENODEV;
+		printk_once("perf/ARM: No irqs for PMU defined, sampling events not supported\n");
+		return 0;
 	}
 
 	irq = platform_get_irq(pmu_device, 0);
@@ -191,6 +191,10 @@ static void cpu_pmu_init(struct arm_pmu *cpu_pmu)
 	/* Ensure the PMU has sane values out of reset. */
 	if (cpu_pmu->reset)
 		on_each_cpu(cpu_pmu->reset, cpu_pmu, 1);
+
+	/* If no interrupts available, set the corresponding capability flag */
+	if (!platform_get_irq(cpu_pmu->plat_device, 0))
+		cpu_pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
 }
 
 /*
--
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