Date:	Fri, 6 Jun 2014 14:13:05 +0200
From:	Ingo Molnar <mingo@...nel.org>
To:	Peter Zijlstra <peterz@...radead.org>
Cc:	Yuyang Du <yuyang.du@...el.com>,
	Dirk Brandewie <dirk.brandewie@...il.com>,
	"Rafael J. Wysocki" <rjw@...ysocki.net>,
	Morten Rasmussen <morten.rasmussen@....com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-pm@...r.kernel.org" <linux-pm@...r.kernel.org>,
	"vincent.guittot@...aro.org" <vincent.guittot@...aro.org>,
	"daniel.lezcano@...aro.org" <daniel.lezcano@...aro.org>,
	"preeti@...ux.vnet.ibm.com" <preeti@...ux.vnet.ibm.com>,
	Dietmar Eggemann <Dietmar.Eggemann@....com>,
	len.brown@...el.com, jacob.jun.pan@...ux.intel.com
Subject: Re: [RFC PATCH 06/16] arm: topology: Define TC2 sched energy and
 provide it to scheduler


* Peter Zijlstra <peterz@...radead.org> wrote:

> > Voltage is combined with frequency, roughly, voltage is 
> > proportional to freuquecy, so roughly, power is proportionaly to 
> > voltage^3. You
> 
> P ~ V^2, last time I checked.

Yes, that's a good approximation for CMOS gates:

  The switching power dissipated by a chip using static CMOS gates is 
  C·V^2·f, where C is the capacitance being switched per clock cycle, 
  V is the supply voltage, and f is the switching frequency,[1] so 
  this part of the power consumption decreases quadratically with 
  voltage. The formula is not exact however, as many modern chips are 
  not implemented using 100% CMOS, but also use special memory 
  circuits, dynamic logic such as domino logic, etc. Moreover, there 
  is also a static leakage current, which has become more and more 
  accentuated as feature sizes have become smaller (below 90 
  nanometres) and threshold levels lower.

  Accordingly, dynamic voltage scaling is widely used as part of 
  strategies to manage switching power consumption in battery powered 
  devices such as cell phones and laptop computers. Low voltage modes 
  are used in conjunction with lowered clock frequencies to minimize 
  power consumption associated with components such as CPUs and DSPs; 
  only when significant computational power is needed will the voltage 
  and frequency be raised.

  Some peripherals also support low voltage operational modes. For 
  example, low power MMC and SD cards can run at 1.8 V as well as at 
  3.3 V, and driver stacks may conserve power by switching to the 
  lower voltage after detecting a card which supports it.

  When leakage current is a significant factor in terms of power 
  consumption, chips are often designed so that portions of them can 
  be powered completely off. This is not usually viewed as being 
  dynamic voltage scaling, because it is not transparent to software. 
  When sections of chips can be turned off, as for example on TI OMAP3 
  processors, drivers and other support software need to support that.

  http://en.wikipedia.org/wiki/Dynamic_voltage_scaling

Leakage current typically gets higher with higher frequencies, but 
it's also highly process dependent AFAIK.

If switching power dissipation is the main factor in power use, then 
we can essentially assume that P ~ V^2, at the same frequency - and 
scales linearly with frequency - but real work performed also scales 
semi-linearly with frequency for many workloads, so that's an 
invariant for everything except highly memory bound workloads.

Thanks,

	Ingo
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