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Message-ID: <CABPqkBQG=SMvtdvpBMnZx4Etf5rRoy3=K81RLNRcPEgBh7Yqdg@mail.gmail.com>
Date:	Tue, 10 Jun 2014 13:53:45 +0200
From:	Stephane Eranian <eranian@...gle.com>
To:	Peter Zijlstra <peterz@...radead.org>
Cc:	LKML <linux-kernel@...r.kernel.org>,
	"mingo@...e.hu" <mingo@...e.hu>,
	"ak@...ux.intel.com" <ak@...ux.intel.com>,
	Jiri Olsa <jolsa@...hat.com>,
	"Yan, Zheng" <zheng.z.yan@...el.com>,
	Maria Dimakopoulou <maria.n.dimakopoulou@...il.com>
Subject: Re: [PATCH 4/9] perf/x86: add cross-HT counter exclusion infrastructure

On Thu, Jun 5, 2014 at 10:29 AM, Peter Zijlstra <peterz@...radead.org> wrote:
> On Wed, Jun 04, 2014 at 11:34:13PM +0200, Stephane Eranian wrote:
>> @@ -2020,12 +2050,29 @@ static void intel_pmu_cpu_starting(int cpu)
>>
>>       if (x86_pmu.lbr_sel_map)
>>               cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
>> +
>> +     if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
>> +             for_each_cpu(i, topology_thread_cpumask(cpu)) {
>> +                     struct intel_excl_cntrs *c;
>> +
>> +                     c = per_cpu(cpu_hw_events, i).excl_cntrs;
>> +                     if (c && c->core_id == core_id) {
>> +                             cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
>> +                             cpuc->excl_cntrs = c;
>> +                             cpuc->excl_thread_id = 1;
>> +                             break;
>> +                     }
>> +             }
>> +             cpuc->excl_cntrs->core_id = core_id;
>> +             cpuc->excl_cntrs->refcnt++;
>> +     }
>>  }
>
> This hard assumes theres only ever 2 threads, which is true and I
> suppose more in arch/x86 will come apart the moment Intel makes a chip
> with more, still, do we have topology_thread_id() or so to cure this?

I assume your comment is relative to kfree_on_online[].
This code is specific to the HT bug, so yes, it assumes 2 threads and that
only one entry of the two excl_cntrs structs needs to be freed.
Doing otherwise, would require a list and will never be used to its full
potential.
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