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Message-ID: <20140611090509.GC3588@twins.programming.kicks-ass.net>
Date:	Wed, 11 Jun 2014 11:05:09 +0200
From:	Peter Zijlstra <peterz@...radead.org>
To:	Paul Bolle <pebolle@...cali.nl>
Cc:	Waiman Long <Waiman.Long@...com>, Ingo Molnar <mingo@...nel.org>,
	hpa@...or.com, konrad.wilk@...cle.com,
	torvalds@...ux-foundation.org, davej@...hat.com, jeremy@...p.org,
	paulmck@...ux.vnet.ibm.com, raghavendra.kt@...ux.vnet.ibm.com,
	tglx@...utronix.de, oleg@...hat.com, linux-kernel@...r.kernel.org
Subject: Re: [tip:locking/core] x86, locking/rwlocks: Enable qrwlocks on x86

On Wed, Jun 11, 2014 at 10:59:21AM +0200, Peter Zijlstra wrote:
> On Wed, Jun 11, 2014 at 10:14:11AM +0200, Paul Bolle wrote:
> > On Fri, 2014-06-06 at 05:20 -0700, tip-bot for Waiman Long wrote:
> > > +#if !defined(CONFIG_X86_OOSTORE) && !defined(CONFIG_X86_PPRO_FENCE)
> > 
> > X86_OOSTORE was removed in v3.14, see commit 09df7c4c8097 ("x86: Remove
> > CONFIG_X86_OOSTORE"). So the first test can be removed here, as it will
> > always be true. Should I submit the trivial, but probably untested,
> > patch to do that or do you prefer to do that yourself?
> 
> I was completely unaware of that removal. Yeah, I'll queue patch
> removing this new instance of it.
> 
> Good to have it gone though, one little crazy less.

I've queued the below. Thanks!

---
Subject: x86, locking: No more OOSTORE nonsense
From: Peter Zijlstra <peterz@...radead.org>
Date: Wed Jun 11 11:01:45 CEST 2014

Paul reported that X86_OOSTORE is dead, yay! Update a comment and
remove a newly added reference.

Reported-by: Paul Bolle <pebolle@...cali.nl>
Signed-off-by: Peter Zijlstra <peterz@...radead.org>
Link: http://lkml.kernel.org/n/tip-6w40duqjdmo3sslxtvisuh7w@git.kernel.org
---
 arch/x86/include/asm/barrier.h |    2 +-
 arch/x86/include/asm/qrwlock.h |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

--- a/arch/x86/include/asm/barrier.h
+++ b/arch/x86/include/asm/barrier.h
@@ -99,7 +99,7 @@
 #if defined(CONFIG_X86_PPRO_FENCE)
 
 /*
- * For either of these options x86 doesn't have a strong TSO memory
+ * For this option x86 doesn't have a strong TSO memory
  * model and we should fall back to full barriers.
  */
 
--- a/arch/x86/include/asm/qrwlock.h
+++ b/arch/x86/include/asm/qrwlock.h
@@ -3,7 +3,7 @@
 
 #include <asm-generic/qrwlock_types.h>
 
-#if !defined(CONFIG_X86_OOSTORE) && !defined(CONFIG_X86_PPRO_FENCE)
+#ifndef CONFIG_X86_PPRO_FENCE
 #define queue_write_unlock queue_write_unlock
 static inline void queue_write_unlock(struct qrwlock *lock)
 {



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