linux-kernel - Re: [PATCH] perf/x86/intel: ignore CondChgd bit to avoid false NMI handling

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Date:	Wed, 11 Jun 2014 13:05:57 +0100
From:	Matt Fleming <matt@...sole-pimps.org>
To:	Peter Zijlstra <peterz@...radead.org>
Cc:	HATAYAMA Daisuke <d.hatayama@...fujitsu.com>, acme@...nel.org,
	mingo@...hat.com, paulus@...ba.org, hpa@...or.com,
	tglx@...utronix.de, x86@...nel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] perf/x86/intel: ignore CondChgd bit to avoid false NMI
 handling

On Wed, 11 Jun, at 01:54:13PM, Peter Zijlstra wrote:
> 
> Matt found in the MSR listing for GLOBAL_STATUS:
> 
> 63 CondChg: status bits of this register has changed.  If CPUID.0AH: EAX[7:0] > 0
> 
> Which brings us to a grand total of 3 different names for this bit.

Right, I'm flinging emails around to get this fixed in the SDM, so that
the answer to,

Q: "How many kernel developers does it take to find the definition of
this bit?"

is less than 4.

-- 
Matt Fleming, Intel Open Source Technology Center
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