linux-kernel - Re: [PATCH] spi/pxa2xx: fix incorrect SW mode chipselect setting for BayTrail LPSS SPI

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Message-ID: <20140611234212.GR5099@sirena.org.uk>
Date:	Thu, 12 Jun 2014 00:42:12 +0100
From:	Mark Brown <broonie@...nel.org>
To:	Chew Chiau Ee <chiau.ee.chew@...el.com>
Cc:	Eric Miao <eric.y.miao@...il.com>,
	Russell King <linux@....linux.org.uk>,
	Haojian Zhuang <haojian.zhuang@...il.com>,
	Mika Westerberg <mika.westerberg@...ux.intel.com>,
	LKML <linux-kernel@...r.kernel.org>,
	linux-arm-kernel@...ts.infradead.org, linux-spi@...r.kernel.org
Subject: Re: [PATCH] spi/pxa2xx: fix incorrect SW mode chipselect setting for
 BayTrail LPSS SPI

On Wed, Jun 11, 2014 at 11:57:02PM +0800, Chew Chiau Ee wrote:

> It was observed that after module removal followed by insertion,
> the SW mode chipselect is not properly set. Thus causing transfer
> failure due to incorrect CS toggling.

> -	value &= ~SPI_CS_CONTROL_SW_MODE;
> +	orig = value &= ~SPI_CS_CONTROL_SW_MODE;
>  	writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);
>  	value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
>  	if (value != orig) {

This is a *really* non-obvious fix, I'd have expected the original value
to be re-read from the hardware here rather than just tweaked, or at
least some comment explaining what's going on.  Possibly also saving to
a differently named temporary variable would do it but whatever I had to
go look at the context to figure out what was happening and even there I
was unclear.

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