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Message-ID: <539ECA8C.4010007@gmail.com>
Date: Mon, 16 Jun 2014 12:44:28 +0200
From: Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>
To: Antoine Ténart
<antoine.tenart@...e-electrons.com>, tj@...nel.org, kishon@...com
CC: alexandre.belloni@...e-electrons.com,
thomas.petazzoni@...e-electrons.com, zmxu@...vell.com,
jszhang@...vell.com, linux-arm-kernel@...ts.infradead.org,
linux-ide@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v6 6/7] ARM: berlin: add the AHCI node for the BG2Q
On 06/16/2014 12:26 PM, Antoine Ténart wrote:
> The BG2Q has an AHCI SATA controller. Add the corresponding nodes
> (AHCI, PHY) into its device tree.
>
> Signed-off-by: Antoine Ténart <antoine.tenart@...e-electrons.com>
> ---
> arch/arm/boot/dts/berlin2q.dtsi | 28 ++++++++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
> index 635a16a64cb4..3fb0d3935aec 100644
> --- a/arch/arm/boot/dts/berlin2q.dtsi
> +++ b/arch/arm/boot/dts/berlin2q.dtsi
> @@ -303,6 +303,34 @@
> clock-names = "refclk";
> };
>
> + ahci: sata@...000 {
> + compatible = "generic-ahci";
> + reg = <0xe90000 0x1000>;
> + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&chip CLKID_SATA>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + sata0: sata-port@0 {
> + reg = <0>;
> + phys = <&sata_phy 0>;
> + status = "disabled";
> + };
> +
> + sata1: sata-port@1 {
> + reg = <1>;
> + phys = <&sata_phy 1>;
> + status = "disabled";
> + };
> + };
> +
> + sata_phy: phy@...0a0 {
> + compatible = "marvell,berlin-sata-phy";
> + reg = <0xe900a0 0x200>;
Antoine,
I guess you'll also need
clocks = <&chip CLKID_SATA>;
here and corresponding code in the PHY driver.
If SATA PHY is accessing SATA registers, disabling the clock will
most likely lock-up the SoC.
Sebastian
> + #phy-cells = <1>;
> + status = "disabled";
> + };
> +
> apb@...000 {
> compatible = "simple-bus";
> #address-cells = <1>;
>
--
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