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Date:	Mon, 16 Jun 2014 07:56:27 -0700
From:	Sören Brinkmann <>
To:	Jongsung Kim <>
CC:	<>, <>,
	Nicolas Ferre <>,
	"David S. Miller" <>,
	Hayun Hwang <>,
	Youngkyu Choi <>
Subject: Re: [PATCH] net/cadence/macb: clear interrupts simply and correctly

On Mon, 2014-06-16 at 02:00PM +0900, Jongsung Kim wrote:
> On 06/13/2014 12:44 AM, Sören Brinkmann wrote:
> > Hi Jongsung,
> Hi Sören,
> > Does this interrupt need to be enabled? There is nothing checking
> > that bit and handling this IRQ in the handler, AFAICT. And you solve
> > this by simply clearing the bit. So, I wonder whether not enabling this
> > IRQ in the first place would solve things too.
> The driver actually checks the bit, but does not clear it. Disabling the
> "Rx used bit read" interrupt you said may be a solution. However, I think
> it is the better way to clear the exceptional HW-state rather than just to
> mask it.
Hmm, I must have missed that.

> > This is now clearing all IRQ flags which is probably not what we want
> > here. This is handling RX only. We still want the non-RX interrupts to go to
> > the actual interrupt service routing.
> The ISR(Interrupt Status Register) is read only in the interrupt service
> routine, macb_interrupt. But is partially cleared here and there. Further
> handler-functions decide jobs to be done by reading/checking other status
> registers. (e.g., TSR, RSR) So, clearing the ISR after reading looks not
> a bad idea.
But you are clearing _all_ interrupt flags in the RX NAPI handler.
Doesn't that mean we might miss certain events?

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