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Date:	Thu, 19 Jun 2014 21:53:26 +0200
From:	Stephane Eranian <eranian@...gle.com>
To:	Andi Kleen <ak@...ux.intel.com>
Cc:	LKML <linux-kernel@...r.kernel.org>,
	Peter Zijlstra <peterz@...radead.org>,
	"mingo@...e.hu" <mingo@...e.hu>, Joe Mario <jmario@...hat.com>,
	Don Zickus <dzickus@...hat.com>, Jiri Olsa <jolsa@...hat.com>,
	Arnaldo Carvalho de Melo <acme@...hat.com>
Subject: Re: [PATCH 1/2] perf/x86: update Haswell PEBS event constraints

On Thu, Jun 19, 2014 at 8:00 PM, Andi Kleen <ak@...ux.intel.com> wrote:
>
> On Thu, Jun 19, 2014 at 05:58:28PM +0200, Stephane Eranian wrote:
> > The following events support PEBS for all umasks,
> > thus use INTEL_EVENT_CONSTRAINT() instead of
> > INTEL_UEVENT_CONSTRAINT():
> >
> > 0xd1 MEM_LOAD_UOPS_RETIRED
> > 0xd2 MEM_LOAD_UOPS_LLC_HIT_RETIRED
> > 0xd3 MEM_LOAD_UOPS_LLC_MISS_RETIRED
> >
> > For event 0xd0 (MEM_UOPS_RETIRED), the same is true, except
> > we need to distinguish precise store (umask 0x82) from load
> > latency events, thus we keep the breakdown per umask. But all
> > umasks do support PEBS.
>
> I sent a similar patch some time ago
>
> http://lkml.iu.edu/hypermail/linux/kernel/1404.2/01509.html
>
> However these days I'm actually thinking of just getting
> rid of the detailed table except for PREC_DIST. All the PEBS
> controls should be noops if the event does not support PEBS
>
I don't quite understand that.
You need to know which events support PEBS. You need a table
for that. then I think you could drop the counter mask because
with HT on, no mask is needed. When HT is off you need a mask,
but it can be hardcoded for all events, well at least on HSW.
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