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Message-ID: <1403306219-3903-4-git-send-email-tthayer@altera.com>
Date: Fri, 20 Jun 2014 18:16:58 -0500
From: <tthayer@...era.com>
To: <robherring2@...il.com>, <pawel.moll@....com>,
<mark.rutland@....com>, <ijc+devicetree@...lion.org.uk>,
<galak@...eaurora.org>, <rob@...dley.net>,
<linux@....linux.org.uk>, <dinguyen@...era.com>,
<dougthompson@...ssion.com>, <grant.likely@...aro.org>,
<bp@...en8.de>
CC: <devicetree@...r.kernel.org>, <linux-doc@...r.kernel.org>,
<linux-edac@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <tthayer.linux@...il.com>,
<tthayer@...era.com>
Subject: [PATCHv6 2/3] devicetree: Addition of the Altera SDRAM EDAC
From: Thor Thayer <tthayer@...era.com>
v2: Changes to SoC EDAC source code.
v3: Fix typo in device tree documentation.
v4,v5: No changes - bump version for consistency.
v6: Assign ECC registers in SDRAM controller to EDAC
Signed-off-by: Thor Thayer <tthayer@...era.com>
---
.../bindings/arm/altera/socfpga-sdram-edac.txt | 15 +++++++++++++++
arch/arm/boot/dts/socfpga.dtsi | 6 ++++++
2 files changed, 21 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
new file mode 100644
index 0000000..540c9cf
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
@@ -0,0 +1,15 @@
+Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
+
+Required properties:
+- compatible : should contain "altr,sdram-edac";
+- reg : should contain the ECC register range in sdram
+ controller (address and length).
+- interrupts : Should contain the SDRAM ECC IRQ in the
+ appropriate format for the IRQ controller.
+
+Example:
+ sdramedac@0 {
+ compatible = "altr,sdram-edac";
+ reg = <0xffc2502C 0x28>;
+ interrupts = <0 39 4>;
+ };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 310292e..fe9832e 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -687,6 +687,12 @@
reg = <0xffc25000 0x4>;
};
+ sdramedac@0 {
+ compatible = "altr,sdram-edac";
+ reg = <0xffc2502C 0x28>;
+ interrupts = <0 39 4>;
+ };
+
rst: rstmgr@...05000 {
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
--
1.7.9.5
--
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