linux-kernel - Re: [Nouveau] [PATCH v2 2/3] drm/ttm: introduce dma cache sync helpers

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Date:	Fri, 27 Jun 2014 08:08:22 -0400
From:	Rob Clark <robdclark@...il.com>
To:	Alexandre Courbot <gnurou@...il.com>
Cc:	Russell King - ARM Linux <linux@....linux.org.uk>,
	"linux-tegra@...r.kernel.org" <linux-tegra@...r.kernel.org>,
	"nouveau@...ts.freedesktop.org" <nouveau@...ts.freedesktop.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
	Stéphane Marchesin <stephane.marchesin@...il.com>,
	Ben Skeggs <bskeggs@...hat.com>,
	Maarten Lankhorst <maarten.lankhorst@...onical.com>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	Lucas Stach <l.stach@...gutronix.de>
Subject: Re: [Nouveau] [PATCH v2 2/3] drm/ttm: introduce dma cache sync helpers

On Thu, Jun 26, 2014 at 7:17 PM, Alexandre Courbot <gnurou@...il.com> wrote:
> On Fri, Jun 27, 2014 at 1:10 AM, Russell King - ARM Linux
> <linux@....linux.org.uk> wrote:
>> On Thu, Jun 26, 2014 at 11:53:20PM +0900, Alexandre Courbot wrote:
>>> We don't plan to rely on CMA for too long. IOMMU support is on the way
>>> and should make our life easier, although no matter the source of
>>> memory, we will still have the issue of the lowmem mappings.
>>
>> When it comes to DMA memory, talking about lowmem vs highmem is utterly
>> meaningless.
>>
>> The lowmem/highmem split is entirely a software concept and is completely
>> adjustable.  An extreme example is that you can boot any platform with
>> more than 32MB of memory with 32MB of lowmem and the remainder as
>> highmem.
>
> True, but isn't it also the case that all lowmem is already mapped in
> the kernel address space, and that re-mapping this memory with
> different cache settings (e.g. by creating a WC mapping for user-space
> to write into) is undefined on ARM and must be avoided? That is the
> issue I was referring to.
>

dma memory should be removed from the kernel linear map (if needed)..
assuming it is allocated w/ dma api's.

btw, something I've been wondering for a little while, but haven't had
time to investigate.  Not sure if this applies to you as well.  But
seems like I have IOMMU's which can be outer-coherent (snoop L2), but
I *think* they are not inner-coherent (L1).  No idea if current dma
memory code can grok this and only do inner-cache op's..

BR,
-R

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