linux-kernel - Re: [PATCH v7 1/7] phy: add a driver for the Berlin SATA PHY

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Date:	Mon, 30 Jun 2014 20:55:35 +0400
From:	Sergei Shtylyov <sergei.shtylyov@...entembedded.com>
To:	Antoine Ténart 
	<antoine.tenart@...e-electrons.com>,
	Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>
CC:	tj@...nel.org, kishon@...com, thomas.petazzoni@...e-electrons.com,
	zmxu@...vell.com, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org, linux-ide@...r.kernel.org,
	alexandre.belloni@...e-electrons.com, jszhang@...vell.com,
	linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v7 1/7] phy: add a driver for the Berlin SATA PHY

Hello.

On 06/30/2014 07:44 PM, Antoine Ténart wrote:

>>>>> +	/* set the controller speed */
>>>>> +	writel(0x31, ctrl_reg + PORT_SCR_CTL);

>>>>     Value undocumented? Or is this the SATA SControl register by chance?

>>> Some magic is still there...

>> I guess Sergei was referring to AHCI spec here.

    Actually, even to the SATA specs. :-)

>> PORT_SCR bits are documented in AHCI spec as:

>> 7:4 = 0x3 Limit speed negotiation to a rate not greater than Gen3
>>            communication rate.

>> 3:0 = 0x1 Perform interface communication sequence [...]. This is
>>            functionally equivalent to a hard reset [...].

>> So, the question is: Should we really need to reset controller in the
>> PHY driver or is it already done in AHCI common code? At least we
>> should change the comment to something like
>> /* set Gen3 controller speed and perform hard reset */

> I just checked, the AHCI common code has a function to do the reset:
> ahci_reset_controller(). As of the max speed negociation rate, I did not
> see it in the common AHCI functions.

    You've looked in a wrong place -- since SControl is a standard *SATA* 
register, it gets read/written by the libata core. The low-level driver only 
provides scr_{read|write}() methods.

> The eSATA port on the Berlin2Q works without this line, but it may be a
> good idea to keep the max speed negociation rate.

    It's usually libata's task to negotiate the SATA speed.

> Anyway, we can remove the reset part. Nice catch!

    Thanks.

> Antoine

WBR, Sergei

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/